Ultra low-cost ARM MCU arrivesWith prices starting at just 65 cents, the LPC1100 flash-based microcontroller family has the potential to displace 8- and 16-bit MCUs. Designers can now get 32-bit performance, at power levels and prices usually attributed to much lower-performance devices.
Initially announced with 15 members, the LPC1100 family is based on ARM's Cortex-M0 IP core. It offers a seamless entry point for designers currently employing 8- and 16-bit MCUs who are looking to start with the scalable ARM architecture throughout their entire range of product development. With this family, designers can take advantage of today's ARM-based low-power design tools and techniques.
According to NXP, the 50-MHz LPC1100 offers over 45 DMIPS of performance, which compares favorably with the performance of 8-bit MCUs (typically under 1 DMIPS) and 16-bit MCUs (typically 3 to 5 DMIPS). In addition to executing basic control tasks, the LPC1100 can tackle sophisticated algorithms. Hence, shorter time to complete more tasks translates into a lower energy consumption. With extensive power optimization, the MCU can operate at less than 10 mA.
Features of the NXP LPC1100 family of microcontrollers include 32 vectored interrupts, four priority levels, and dedicated interrupts on up to 13 GPIOs; a UART, two 16-bit and two 32-bit timers; power-on-reset and multi-level brown-out-detect, and an eight-channel, 10-bit ADC.
The LPC1100 family is supported by development tools from IAR, Keil, Hitex, and Code Red. NXP will offer an easy to use, comprehensive development tool platform for under $30. Pricing (in 10,000-piece quantities) for the 33-pin package is: LPC1111FHN33/101 at $0.65, LPC1112FHN33/101 at $0.75, LPC1113FHN33/201 at $0.85, and LPC1114FHN33/201 at $0.95, with flash sizes of 8k, 16k, 24k, and 32Kk respectively. In addition, 48-pin LPQFP and PLCC44 packages will be available for socketed applications. All the devices will be available in early December. More information is available at www.standardics.nxp.com/microcontrollers.