Four steps predict design times for building large asicsIntel has developed a four-stage design process to get more predictability into building large asics.
Originally developed for internal projects based on split teams, such as its PC chipsets, the company's new microelectronics services group will use the process to build customer designs and provide information on progress using secure websites.
The group has four design centres around the world, and will take designs from the RTL [logic-level design] stage through to tapeout, but will organise manufacturing and packaging. Intel has enlisted Synopsys to provide front-end design from the architectural to the RTL stage.
Naveed Sherwani, general manager of Intel Microelectronics Services, said: "We are using open methods. Traditional asic design is a black box. We have a website with data on the project that is available 24-7.
"When doing designs for internal customers, we came up with the idea that using humans for feedback is not a good idea. You get perceptions rather than reality.
"Most customers are using single flows and making multiple iterations. Our method is to break it down into four stages and go through in a systematic fashion."
The four stages are used to give customers an idea of how far a design is from tapeout and are named in credit-card style from bronze to platinum.
"We have an automated way of determining which stage the design is in," said Sherwani.
As the design progresses from bronze to platinum, the timing guarantees get more accurate until there are no timing issues remaining. Intel uses this to determine the effect of an engineering change order (ECO). If it sends the design back to an earlier stage, then the time to complete that stage needs to be added again.
The design starts off at bronze, which is where all design-related issues are ironed out.
"Further stages are refinements," said Sherwani. "If you are in gold and you get an ECO that puts you back to silver, and you know that silver takes two weeks, it gives the customer a clear idea of whether that feature should be included or not."
Sherwani says the group has adopted a hierarchical flow and uses equivalency checking techniques to make sure designs stay consistent as they move between stages.