DRAM MIMCAP process is next focus for IMEC 32-nm project

John Walko

October 16, 2007

John Walko

LONDON — Belgian research organization IMEC has extended its work on 32-nm CMOS device scaling to include a project on DRAM MIMCAP (metal-insulator-metal capacitors) process technology.

The group says it will allow it and its many partners in the 32-nm program to address the material and integration requirements for scaling DRAM MIMCAP to future technology generations.

The sub 32-nm CMOS device scaling program brings together the leading five memory suppliers together with the world’s leading logic IDMs and foundries including STMicroelectronics, NXP, Elpida, Hynix, Infineon/Qimonda, Intel, Micron, Panasonic, Samsung, , Texas Instruments and TSMC.

The latest project builds on an earlier extension of the IMEC program, which is its traditional logic- and SRAM-oriented work. The objective of the sub-program is to research high-k and metal gate options sustaining a DRAM-oriented process flow.

The researchers note that to scale DRAM towards the 50nm node and beyond, MIMCAP dielectrics require materials with a higher dielectric constant compared to current industrial materials such as ZrO2. They are targeting, by mid 2008, an effective oxide thickness of 0.5nm for the MIMCAP dielectric in the sub-50nm technology node, going down to 0.3nm in 2009 for the sub-45nm node.

They add scaling the dielectric equivalent oxide thickness while attaining very low leakage currents is one of the major bottlenecks facing the DRAM manufacturing industry.

In the first instance, a baseline process for MIMCAP evaluation will be formulated on TiN electrodes and ZrO2 as the capacitor dielectric. This process will be used as a vehicle for screening new electrode materials such as W, Mo, TaC and Ru.

In the next phase new material stacks combining high-k and electrodes will be screened theoretically and experimentally for potential integration. The stringent DRAM specifications as dictated by the ITRS will be used as selection criteria. They include leakage current lower than 1fA/cell and a total physical MIM thickness smaller than 20nm.

Finally, a MIMCAP deposition process will be developed looking at major integration issues and mimicking as far as possible the effect of full DRAM integration such as passivation. MIMCAP test structures will be integrated and characterized on electrical and reliability performance.

Both MOCVD (metal-organic chemical vapor deposition) and ALD (atomic-layer deposition) will be used since they allow depositing high-quality thin films.