AMD, not ARM, first to use startup's low-power clock IP
LONDON – Advanced Micro Devices Inc. has achieved the first commercial implementation of resonant clock mesh technology licensed from startup company Cyclos Semiconductor Inc.
Cyclos (Berkeley, Calif.) said that the AMD (Sunnyvale, Calif.) has used the power-saving clock distribution technology in x86-compatible processor cores destined for inclusion in Opteron server processors and client Accelerated Processing Units (APUs). Cyclos engaged with processor technology licensor ARM Holdings plc in the early years of its existence driving an expectation that an ARM processor core would be the first commercial demonstration of the technology.
However it is AMD's Piledriver 64-bit core, which operates at up to and in excess of 4-GHz clock frequency, that represents the first volume production-enabled implementation of resonant clock mesh technology, Cyclos said. Piledriver, fabricated in a 32-nm CMOS process, employs the resonant clocking to reduce clock distribution power by up to 24 percent, while maintaining previous clock-skew targets, Cylos said.
The Cyclos resonant clock mesh technology employs on-chip inductors arranged to interact with the large capacitance of the clock signal distribution network to form an oscillating "tank circuit." The result is that Cyclos inductors and clock control circuits "recycle" the clock power instead of dissipating it on every clock cycle as conventional clock tree implementations do. The result is a reduction in total IC power consumption of up to 10 percent, Cyclos said.
Cyclos was founded in 2006 as a spin out of the University of Michigan. The company is now based in Berkeley, California with an office in Ann Arbor, Michigan. Cyclos licenses resonant clock mesh semiconductor IP, design automation tools, and provides consulting services for resonant clock mesh design. Cyclos announced a proof of concept processor implementation based on the ARM926EJ-processor in 2008 under the name "Project Elizabeth" along with the availability of design tool support.
"We were able to seamlessly integrate the Cyclos IP into our existing clock mesh design process so there was no risk to our development schedule," said Samuel Naffziger, corporate fellow at AMD, in a statement issued by Cyclos. "Silicon results met our power reduction expectations, we incurred no increase in silicon area, and we were able to use our standard manufacturing process, so the investment and risk in adopting resonant clock mesh technology was well worth it as all of our customers are clamoring for more energy efficient processor designs."
In the same statement, Linley Gwennap, principal analyst of The Linley Group, said: "This announcement proves that the Cyclos resonant clock mesh technology provides meaningful power savings in real-world products. We expect other processor designers to adopt the Cyclos technology in applications where power reduction is important."
The company is led by Marios Papaefthymiou, founder and president; Alexander Ishii, vice president of engineering; and Dan Ganousis, vice president of business development.
"We believe resonant clock mesh design will be a key enabler for GHz+ embedded processor IP blocks in next generation SoCs that also require ultra-low power consumption," said Papaefthymiou, in the company's statement.
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