ARM, Cadence tune support for processor design
LONDON – Processor IP licensor ARM Holdings plc and EDA software vendor Cadence Design Systems Inc. have said they have been working together to link ARM's processor optimization packages (POPs) to Cadence's software for digital design called Encounter.
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The combination produces further improvements in performance and power consumption trade offs for system-chips (SoCs) based on Cortex A-series processor cores, the companies said. No comment was made as to the design quality achieved with POPs when linked to design tools from other EDA vendors, such as Synopsys.
ARM which licenses processor architectures and core designs at the logical level also provides physical IP that can be used to construct the transistor detail of processors on particular CMOS manufacturing processes. However, such design detail can be time consuming and so recently ARM has begun providing processor optimization packages that provide the detailed design and allow options for developers to move away from the reference and make changes. With most of the work already done this speeds up design and improves time to market.
However, for system-on-chip designs the processor and its optimization have to be considered in the SoC context.
Cadence and ARM have come up with an initial approach for the Cortex-A9 processor on the 40LP 40-nm manufacturing process technology, including low threshold voltage, from foundry Taiwan Semiconductor Manufacturing Co. Ltd. The collaboration is being extended to the 28HPM process form TSMC and to include single, dual and quad-core implementations of Cortex-A9 and Cortex-A15 processors.
John Heinlein, vice president of marketing for the physical IP division at ARM, said that the work between Cadence and ARM provides "higher performance at a lower power than previously available."
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