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Broadcom samples dual control/data plane net CPUs

October 03, 2012

Bernard Cole-October 03, 2012

San Jose, Ca. – Through its just acquired NetLogic group Broadcom has started sampling a 28-nm network processor family, the XLP 200, which combines control as well as data plane processing as well as a new accelerator block for handling some security features.

The chip family will come in versions that will include one or two custom out-of-order MIPS cores that support four threads each at up to 2 GHz. They will also have a built-in a grammar processing engine that links incoming packets to the appropriate malware database for security searches, a function previously handled in software on general purpose cores.

The chips also include hardware accelerators for deep packet inspection and regular expression computations. The accelerators act independently, requiring no help from the chip’s general-purpose MIPS cores.

Being sampled now, the chips are expected to be in full volume production by the second half of 2013. The former NetLogic group has a family of higher-end 40nm chips using more MIPS cores, targeted primarily at data plane processing.

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