Design Con 2015

Cadence tapes out 14nm ARM test chip with IBM FinFETs

October 31, 2012

Bernard Cole-October 31, 2012

At the ARM Technical Conference in Santa Clara, Ca., Cadence Design Systems announced tape out of a 14-nanometer test-chip featuring an ARM Cortex-M0 processor fabricated using IBM’s FinFET process technology.

The 14-nanometer milestone is the most recent as part of a multi-year agreement between ARM, Cadence and IBM to develop systems-on-chip (SoCs) at the advanced process nodes of 14 nanometers and beyond. SoCs designed at 14 nanometers with FinFET technology offer the promise of a significant reduction in power consumption.

“FinFET designs offer significant advantages to the design community,” said Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence, “but also require advanced foundry support, IP and EDA technology to meet the considerable challenges.

The chip was developed to validate the building blocks of foundation IP for 14-nanometer design. In addition to the ARM processor, SRAM memory blocks and other blocks were included that provide the characterization data necessary for foundation IP development for FinFET-based ARM Artisan physical IP.

“Each move to smaller geometry brings new challenges that require deep collaboration among ecosystem leaders in the SoC design chain,” said Dipesh Patel, vice president and general manager, Physical IP Division at ARM.

ARM design engineers incorporated an ARM Cortex-M0 processor using 14-nanometer FinFET technology built on IBM’s silicon-on-insulator (SOI) technology, which offers an optimal performance/power profile. A comprehensive 14-nanometer double patterning and FinFET support methodology was employed, with engineers using Cadence technology to design the FinFET 3D transistor chip.

According to Gary Patton, vice president of IBM Semiconductor Research and Development Center, to succeed, engineers required support for 14-nanometer and FinFET rule decks, as well as enhanced timing analysis.

The chip was implemented using the Cadence Encounter Digital Implementation (EDI) System with ARM 8-track 14-nanometer FinFET standard cell libraries designed with Cadence Virtuoso tools.

It provides advanced digital capability required for implementing designs based on 14-nanometer FinFET-based DRC rules, and incorporates new GigaOpt optimization technology to realize power and performance benefits offered by FinFET technology. The design also used production-proven double patterning-correct implementation capabilities

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