Building quality & signal integrity into PoP-based PCB design & assemblyEditor's note: This article addresses the need for designers of printed circuit boards for nextgen ICs to be savvy about package-on-package technology.
New ways of working with sub-assembly printed circuit board (PCB) design and assembly have become necessary to design effectively for the new era of package-on-package (PoP) technology. Following the new design guidelines and assembly procedures for high density ICs fabricated with nanometer-scale geometries will assure that an OEM’s product will meet its performance objectives.
There are multiple factors involved, and each plays a significant role in efficiently designing and assembling PoP-based PCBs. Among them are high reliability, excellent signal integrity, design for assembly (DFA), and state-of-the-art pick and place on the assembly floor.
At the Trace Level
Maintaining high reliability for BGA-based PoP board design starts at the trace level. A good guideline to follow is to have only one trace between two BGA pads because two traces pose manufacturing difficulties. Also, board fabrication challenges arise when running multiple thin 2-to-3 mil traces between two BGA pads. Further issues surface if the length of those thin traces is too long, and if those types of traces are spread throughout the board.
Ideal traces are 5 mils or thereabouts. Generally, they are highly acceptable as good manufacturing practice. However, in today’s world of miniaturization, those 5 mil traces may not be practical or possible. In the small PCB world requiring PoP, high reliability and excellent signal integrity demand that a single trace be no more than 2.5 to 3 mils between BGA pads, as shown in Figure 1.
Figure 1: High reliability and excellent signal integrity demand that a single trace be no more than 2.5 to 3 mils between BGA pads.
Other design factors include blind vias, solid ground planes, and decoupling capacitors. Buried vias are to be avoided as much as possible. Blind vias are okay to use because they are easier to work with during manufacturing. On the other hand, buried vias are difficult because they require one further lamination cycle. Also, it’s important to use solid ground planes as much as possible to maintain ultra-clean noise suppression and keep signal-to-noise ratio (SNR) under control.
As shown in Figure 2, keeping decoupling capacitors as close as possible to BGA balls holds true with PoP more than ever before for high signal integrity, especially if a high speed layer is involved. The PCB designer needs to make sure decoupling capacitor distance between the capacitor and the BGA ball is as short as possible, keeping signal distance between points A and B as short as possible.
Figure 2: Decoupling caps placed closed to the BGA pins in a via-in-pad design
One decoupling capacitor can support up to three BGA balls. The PCB designer needs to make sure there are enough decoupling capacitors to assure all of them are properly decoupled. If sufficient decoupling capacitors aren’t available, the probability increases of getting a signal considerably noisier and more out of control than expected.
Tracking PoP Through Assembly
Standard operating procedure for the PCB designer is to take the lead in anticipating unforeseen issues that his or her design can encounter at assembly. Early on, the savvy designer works to avoid such issues, and, collaborating with assembly engineering, tracks them so that manufacturing steps are performed without troublesome and costly glitches. With a PoP-based PCB design, this phase is especially critical. The ultimate goal is to make these PoP assemblies reliable, repeatable, and also make certain that the project can be successfully transferred from prototype to production level.
Pick and place is especially important for the PCB designer, particularly the dip unit and the mount head used for PoP placement accuracy - for example, the scatter chart in micrometers. Figure 3 shows the result of a placement accuracy measurement on a MYDATA pick and place machine.
Figure 3: Scatter Chart (Image courtesy of Micronic MYDATA AB)
Each dot represents the deviation from nominal position in x and y for one placement. The dotted rectangle represents the specification limit corresponding to Cpk=1.33, and the two dotted lines represent the average offset. The result is obtained by placing glass slug components with a BGA pattern on a glass plate, and then measuring the position of each component in a Nikon measurement machine.
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