Design Con 2015

ARM, Synopsys team on ARM Cortex-A reference platforms

March 25, 2013

Bernard Cole-March 25, 2013

ARM Ltd. and Synopsys  have just announced availability of a jointly developed optimized 28-nanometer (nm) reference implementations for ARM Cortex-A15 MPCore and Cortex-A7 MPCore processor clusters as well as the CoreLink CCI-400 cache-coherent interconnect.

The companies collaborated to deliver these optimized implementations in TSMC 28HPM process technology using the Synopsys Galaxy Implementation Platform, ARM Artisan standard cells and memories, and ARM POP technology for core-hardening acceleration specifically optimized for Cortex-A15 and Cortex-A7 processor implementations.

According to Tom Cronk, executive vice president and general manager, Processor Division at ARM, system-on-a-chip (SoC) designers can use these reference implementations to create high-performance Cortex-A15 and energy-efficient Cortex-A7 processor clusters, and can combine them with the CCI-400 interconnect to create a big.LITTLE processing system that delivers increased product functionality with longer battery life.

“With a diverse range of products expected in today’s end markets, ARM Powered® solutions need to be optimized across a spectrum of energy-efficiency and high-performance targets,” he said.

Configured for ARM Cortex-A15 and Cortex-A7 processors as well as CCI-400 interconnect, the Synopsys Reference Implementations provide tool scripts, a baseline floorplan, design constraints and documentation to serve as an optimized starting point for implementation.

These scripts, built on the widely-used Synopsys tool Reference Methodologies (RMs) and optimized for high-performance cores, leverage Galaxy Platform capabilities such as Design Compiler Graphical physical guidance for improved timing and post-route correlation.

The scripts also leverage IC Compiler technologies, including final-stage leakage recovery for reduced leakage power, data flow analysis for faster floorplan creation and transparent interface optimization for faster top-level closure.

They are configured for TSMC 28HPM process technology with ARM Artisan standard cells, memories and ARM POP technology. Designers may further optimize the scripts for their own design goals, processor configurations, process technologies and libraries.

The Synopsys Reference Implementation for the Cortex-A7 processor cluster is for a quad-core MPCore configuration, optimized first for energy efficiency, then for maximum speed to provide energy-efficient multi-processing.

ARM and Synopsys have also collaborated on a reference verification platform for Synopsys Discovery Verification IP, which supports the ARM AMBA 4 ACE protocol and CCI-400 interconnect. With this reference verification platform, said Cronk, verification engineers can rapidly develop highly efficient verification environments for their cache-coherent designs.

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