Micron’s DRAM cube: how it almost did not happen

Rick Merritt

August 13, 2013

Rick MerrittAugust 13, 2013

SAN JOSE, Calif. — Micron's Hybrid Memory Cube -- a 4 GByte stack of DRAM die on a 160 GByte/second interface now sampling to a few close partners -- almost didn't happen. The first prototype failed to make connections between the DRAM stack and a controller inside the package, forcing an all-hands-on-deck effort to save the project.

Two top engineering managers leading the program told some of the story behind the Cube in an interview with EE Times. They also shared a few of their goals for the next-generation chip now in the works -- an 8 GByte stack transferring data at up to 320 GBytes/second with even greater power efficiency that the current samples.

The Cube got its start in early 2006 when the industry was buzzing with talk both about multicore processors and 3D chip stacks using through silicon vias (TSVs).

"We had low-density TSV capability called through-wafer interconnect deployed in some CMOS imager chips," said Brent Keeth, a Micron Fellow and DRAM design group leader. "CPU road maps made it clear the number of cores was growing rapidly, and traditional DDR interfaces with their limited bandwidth seemed ill-suited to the performance requirements -- the memory wall was getting taller and thicker," Keeth said.

"As Brent was working through a tiled structure for DRAMs with greater concurrency, we'd go back and forth on how the trade-offs between it and a controller played off against each other," said Joe Jeddeloh, general manager of a logic design group at Micron that had developed DDR chip sets as well as controllers for PCI Express and solid-state drives.

Keeth and Jeddeloh developed a proposal to make a Gen-1 prototype that would deliver 128 GBytes/second. "When we started pitching this internally it started selling itself [because] our performance target was astonishingly high, and the kinds of problems it solved got people spun up," said Keeth.

Representatives from Micron's assembly R&D team joined the DRAM and logic engineering managers in a meeting with Micron vice president Brian Shirley and others, going over "a pretty large Powerpoint" presentation they had developed.

"Within the day we had a green light" to build the prototype, said Keeth, noting plenty of engineers had been involved for some time in the discussions. "We weren't hitting them cold with this information," he said.

About a year later, Micron hosted one of several industry meetings kicked off by US government technologists about the need for Exascale-class supercomputers. Representatives from top government research labs and agencies crowded into Micron's executive board room along with a cross-section of industry technologists. The meeting was one of the first where Micron talked about its 3D plans with people outside the company.

"There were various presentations on TSVs, power, and why traditional memory wouldn’t work," Keeth recalled. "They had their own ideas, but they deferred to us to solve the problem and that gave us a lot of momentum," he said.

Not long after the Exascale meeting, the prototype came back from the fab. It didn't work. Keeth said:

Assumptions we made were wrong, so we had to adapt the design to the sheer number of TSVs [required as well as] back-end jobs in thinning and stacking wafers. Our TSV technology when we started was not geared to solve this problem, so we had to get support from the company to [develop a capability to] handle thousands of interconnects from die to die.

Specifically, "the TSVs in the logic layer didn't show up as planned, so we had to restructure how we put the Cube together to get a functional prototype -- there was some reactionary engineering that was well executed," recalled Jeddeloh.

The Cube required thousands of TSVs, many more than Micron used on past CMOS imagers.
The Cube required thousands of TSVs, many more than Micron used on past CMOS imagers.

Engineers spent most of 2008 figuring out a way to get the TSVs to connect the logic die to the DRAM stack so the memories could get the power they needed.

Ultimately they created a "larger than life, sacrificial logic die bound down to a substrate, then put the DRAM stack underneath it" rather than on top as originally envisioned, said Keeth. The two parts were placed "in a ceramic package with a cavity containing the logic on top, close to lid so power from solder balls on the logic die could connect easier, face-to-face, using a bridge network with balls to bring power," he said.

It was "a monumental recovery -- a big catch in the end zone that salvaged the program," he added.

"That all got us through the gate, showing our ability to build TSVs with yield and thin the wafer stacks," said Jeddeloh. "At that point, we got approval to build the first actual product, the Gen-2 design" now sampling to first customers.

To read more, go to: “Make tools play nice.

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