MathWorks couples Xilinx FPGAs to Simulink

Ron Wilson Xilinx

June 2, 2011

Ron Wilson

In design of algorithm-intensive ICs, simulation at high levels of abstraction is mandatory. Simulation begins at the mathematical level, testing algorithms against data sets. It ends with net list-level functional verification runs. Tools for both of these undertakings are well-understood. The challenge comes in between, when parts of the design remain in algorithmic form, parts are under development as behavioral or transaction-level code such as SystemC, and reused IP blocks already exist in RTL. Even in a multi-mode simulation environment, traversing a test case can be crushingly slow, dragged down by the level of detail in the RTL simulation.

MathWorks has clearly encountered this issue when customers use the Simulink co-simulation block. Efficiently handling transactions between simulators doesn't make the simulations run faster. In response, the company today introduced EDA Simulator Link 3.3, with the ability to couple an FPGA emulation - via any of several Xilinx development boars - into the Simulink co-simulation environment.

Ken Karnofsky, director of marketing at MathWorks, explained the approach. A user would select a supported Spartan or Virtex board and install it in the normal way. Then the team would select the RTL they intend to put in the FPGA - either existing design RTL, test-bench code, or algorithmic RTL created by the MathWorks HDL code generator. This code goes through the normal Xilinx tool chain, along with interface code to connect to Simulink, and from there in to the FPGA. Simulink then executes transactions with the FPGA as if the chip were an external simulator.

The FPGA operates at full hardware speed, producing transactions orders of magnitude faster than an RTL simulation. There are limitations in controlability and observability, as there would be for any FPGA emulation. It appears that the designers must define ahead of time the transactions between Simulink and the FPGA. And Karnofsky said the approach requires familiarity with FPGA use, since after all the team is taking an RTL design through the Xilinx design flow.

EDA Simulator Link 3.3, with FPGA-in-the-loop capability and connections for Cadence Incisive Enterprise Simulator and Mentor's ModelSim and Questa, is available now, with list prices starting at $2,000 US.