Next-gen SmartFusion2 SoC FPGA boasts breakthru security, reliability, and low powerMicrosemi Corporation's SmartFusion2 system-on-chip (SoC) field programmable gate array (FPGA) family is designed to address fundamental requirements for advanced security, high reliability, and low power in critical industrial, defense, aviation, communications and medical applications. SmartFusion2 integrates inherently reliable flash-based FPGA fabric, a 166 megahertz (MHz) ARM Cortex-M3 processor, advanced security processing accelerators, DSP blocks, SRAM, eNVM and industry-required high-performance communication interfaces all on a single chip.
SmartFusion2 provides the most advanced design and data security capabilities starting with a robust root-of-trust device with secure key storage capability using what Microsemi claims is the SoC FPGA industry’s only physically unclonable function (PUF) key enrollment and regeneration capability. SmartFusion2 is also claimed to be the only SoC FPGA protected from differential power analysis (DPA) attacks using technology from the Cryptographic Research Incorporated (CRI) portfolio. Users may also leverage built-in cryptographic processing accelerators including: advanced encryption standard (AES) AES-256, secure hash algorithm (SHA) SHA-256, 384 bit elliptical curve cryptographic (ECC) engine and a non-deterministic random bit generator (NRBG).
Smartfusion2 devices are designed to meet many industry standards including IEC 61508, DO254 and DO178B, and feature SEU immunity of zero failures in time (FIT). As an additional benefit, SmartFusion2 flash FPGA fabric does not require external configuration, which provides an added level of security since the SoC FPGA retains its configuration when powered off and enables device “instant-on” performance.
SmartFusion2 protects all its SoC embedded SRAM memories from SEU errors. This is accomplished through the use of single error correction, double error detection (SECDED) protection on embedded memories such as the Cortex-M3 embedded scratch pad memory, Ethernet, CAN and USB buffers, and is optional on the DDR memory controllers.
SmartFusion2 devices are available with a range of density from 5K LUT to 120K LUT plus embedded memory and multiple accumulate blocks for digital signal processing (DSP). High bandwidth interfaces include PCI Express (PCIe) with flexible 5G SERDES along with high-speed double data rate DDR2/DDR3 memory controllers. The device also includes a microprocessor sub-system (MSS) with a 166 MHz ARM Cortex-M3 processor, on chip 64KB eSRAM and 512KB eNVM to minimize total system cost. The MSS is enhanced with an embedded trace macrocell (ETM), 8 Kbyte instruction cache, and peripherals including controller area network (CAN), Gigabit Ethernet and high speed USB 2.0. Optional security accelerators can be used for data security applications.