Tool speeds register verification

May 26, 2015

Max The Magnificent-May 26, 2015

Agnisys is well known for its IDesignSpec register generator design tool. IDesignSpec is available as a plug-in for popular editors that are commonly used to document registers (Microsoft Word, Microsoft Excel) and as a command line utility for the Windows, Linux, and Solaris platforms.

It imports various formats (e.g., IP-XACT, SystemRDL, XML, CSV) and allows FPGA, SoC, and IP designers to create the register map specification for their digital system and automatically generate all of the required outputs from it (these outputs include UVM, OVM, RALF, SystemRDL, IP-XACT, and user-defined outputs created using Tcl or XSLT scripts).

Register verification is a significant part of the design verification problem. It is one of the first aspects of the design that must be tested because the registers contain the configuration settings for the hardware and are the basis of the hardware / software interface. Thus, the rest of the design's functionality depends on the accuracy of the register implementation.

In order to address this portion of the design flow, Agnisys has announced the availability of its ARV (Automatic Register Verification) add-on that enhances the IDesignSpec register specification solution with the capability to automate the register verification process.

ARV comes in two configurations as follows:

  • ARV-Formal takes the register specification and RTL design as input and performs a formal proof to ensure all register operations conform to the specification. ARV-Formal is powered by 360-DV LaunchPad -- an adaptive formal technology platform from OneSpin Solutions. ARV-Formal automatically generates assertions directly from the specification and executes them using the integrated formal engine, therefore completely automating setup. 
     
  • ARV-Sim is a complete register verification solution that integrates with the Synopsys VCS, Cadence Incisive, and Mentor Questa simulators. ARV-Sim completely automates the UVM verification process and eliminates the lengthy and error prone UVM test bench and sequence creation process. ARV-Sim provides positive and negative sequences automatically -- the actual test sequences that stimulate the hardware to ensure that the implementation is correct. In addition to testing the register implementation, ARV-Sim also verifies the interface between the registers and the application logic.
 

Continue reading on Embedded's sister site, EE Times: "New tool automates register verification process for FPGA, SoC & IP designs."

 

Loading comments...