Design Con 2015

6.375-Gbit/s SerDes features waveform viewing technology

August 17, 2008

ismini.scouras-August 17, 2008

Camarillo, Calif.—Vitesse Semiconductor Corp. is getting ready to sample a multi-protocol, 6.375-Gbit/s multi-rate SerDes transceiver.

The VSC3441 is well suited for next-generation backplanes and communication equipment running multiple protocols, including Gigabit Ethernet, XAUI, 2xXAUI, Fibre Channel, Serial Attached SCSI (SAS), Serial ATA (SATA), Serial Rapid IO, Infiniband and PCI Express (PCIe).

The VSC3441 operates at selected data rates from 125 Mbit/s to 6.375 Gbit/s and incorporates advanced equalization to compensate for various impairments and losses encountered in copper cables, backplane traces and connectors. The device combines integrated technologies: SerDes, Clock and Data Recovery (CDR) and advanced signal equalization. It is also the first high-speed SerDes to incorporate Vitesse's VScope waveform viewing technology, which enables a real-time oscilloscope view of the received data, providing telemetry of high-speed signals.

The VSC3441 allows OEMs to serialize data to higher rates for simplified transmission through legacy backplanes or cable interconnects. This is achieved by compensating for the signal path degradation which, in turn, improves the signal integrity performance of the transmission. The integrated VScope waveform viewing technology is then used by OEMs for real-time system diagnostics and remote monitoring functions in these applications. The result: a state-of-the-art signal integrity solution that extends the use of existing ASICs and FPGAs with slower speed interfaces.

With a single reference clock input, the VSC3441 provides a high degree of signal integrity through a configurable input and output equalization. In various modes, the VSC3441 can function as a single 20:1 SerDes with redundant I/O, a dual 10:1 SerDes with redundant I/O, and a quad 10:1 serializer or quad 1:10 deserializer. The high-speed CDR per channel removes random jitter from optical fiber links. I/O characteristics are programmable for interfacing to a wide variety of devices and protocols.

The device will be available in a 196-pin, 15mmx15mm flip chip ball grid array (FCBGA) package.

Pricing: $32 in volume.
Availability: General samples will be available in the fourth quarter of 2008.
Datasheet: Click here.

Vitesse, www.vitesse.com

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