Whoosh! Altera demos next-gen 25-Gbps FPGA transceivers

Clive Maxfield

September 20, 2010

Clive Maxfield

The folks at Altera have great big smiles on their faces today, because they've achieved a significant milestone in transceiver technology by becoming the first company to successfully demonstrate 25-Gbps transceiver performance in programmable logic.

They achieved this with their 28-nm transceiver test chip, a prototyping platform that they are using to deploy 28-Gbps transceivers on 28-nm FPGAs. Reaching the 25-Gbps milestone more than doubles the transceiver performance in currently available FPGA solutions, and rivals or exceeds the abilities of competitive ASSP offerings.

The latest in a series of 28-nm test chips, this device provides insight into how high-performance transceiver designs behave on TSMC's leading-edge 28-nm high-performance (HP) process. The results from this test chip will be used to develop and apply optimization techniques for power, jitter, and link performance in the production tape-out of Stratix V FPGAs featuring 28-Gbps transceivers.

Altera's forthcoming Stratix V FPGAs are being architected to serve markets that require very high performance at fixed cost and power budgets, such as military communications, optical transmission networks and emerging test equipment systems.

28-nm transceiver test chip demonstration video
A demonstration video showing Altera's 28-nm transceiver test chip running a pseudo-random bit pattern at 25 Gbps is currently available on Altera's website at www.altera.com. The demonstration video also includes a look at both transmit and receive eye diagrams across a 10GBASE-KR backplane running at 10.3 Gbps.


But wait, there's more
For the highest data rate and bandwidth applications there is a trend toward 100 Gigabit Ethernet. To implement this most efficiently, optical interfaces are moving to 4 x 25 Gbps and 4 x 28 Gbps channels.  Achieving these data rates in today's Stratix IV-GT devices, which are implemented at the 40-nm technology node, would require 10 x 11.3 GBps channels. By comparison, achieving the same data rates in Altera's next-generation Stratix-V FPGAs, which will be implemented at the 28-nm technology node, will require only 4 x 28 Gbps channels.
 

Changing the interface from 10 x 11.3 Gbps channels to 4 x 28 GBps channels enable greater system integration and lower system cost (the size and cost of the optical module will be reduced by 30 to 40%). This next-generation implementation will also offer significantly better power efficiency (per Gbps).

When Stratix V FPGAs are presented to the market, the GX and GS versions will support up to 66 x 12.5 Gbps channels (each of which can support a wide data range capability of 600 Mbps to 12.5 Gbps). By comparison, the GT versions will support up to 32 x 12.5 Gbps channels PLUS 4 x 28 Gbps channels (each of which can support a data range capability of 20 to 28 Gbps).


In addition to chip-to-chip, and chip-to-optical module type applications, the 12.5 Gbps channels can also be used for 10GBASE-KR backplane applications up to 12.5 Gbps. By comparison, the 28 Gbps channels will initially be used only for chip-to-chip, and chip-to-optical module applications.

In the case of the 12.5 Gbps channels, the receivers also feature a very clever feature called the EyeQ eye viewer (I love the name). In addition to allowing users to access the eye diagram actually seen inside the chip, Altera use this technology to support dynamic reconfiguration of the receiver equalization.


My thought is that users could extend this capability by establishing a feedback path to the transmitting device and using this feedback to implement dynamic reconfiguration of the transmitter's pre-emphasis. This would be an extremely useful capability in the case of line cards in communications applications where cards can be pulled out and new cards populated in different slots... but we digress...

Returning to the 28 Gbps channels, it boggles the mind when you start to think about how to overcome the parasitic effects that will quickly degrade signal quality if they are not brought under control. In fact one way these effects are controlled is for an integrated inductor to be embedded under each 28G bump so as to tune out parasitic loading. This also explains why Altera has been strategically investing in RF design technologies, but that's a story for another day...


The bottom line is that Altera have demonstrated something very exciting – I can’t wait for the final production devices to reach the market and to see the amazing things designers create using them.