Renesas SoC targets high-end automotive nav and infotainment

March 26, 2013

Toni_McConnel-March 26, 2013

The R-Car H2 is a new member of the R-Car Series of automotive Systems-on-Chip (SoCs) from Renesas Electronics Corporation. Capable of delivering more than 25,000 DMIPS, the R-Car H2 provides high performance and state-of-the-art 3D graphics capabilities for high-end multimedia and navigation automotive systems. The R-Car H2 is powered by the ARM CortexA-15 quad-core configuration running an additional ARM CortexA-7 quad-core – which the company claims is the industry’s first implementation of a Quad ARM Cortex A15 and the big.LITTLE processing technique in an automotive SoC.

The new SoC's media hardware accelerators enable features like 4 x HD 1080p video en/decoding, including Blu-Ray support at 60 frames per second, image/voice recognition and high-resolution 3D graphics with almost no CPU load. These implemented hardware modules also execute the display content improvements needed for human-machine interface (HMI)/navigation data in parallel to Movie/DVD handling.


Renesas’ IMP-X4 core, implemented in R-Car H2 as an optional feature, provides real-time image processing that enables developers to support the emerging trend of augmented reality. In order to fully benefit from the IMP-X4 core, the R-Car H2 also supports up to four independent input camera channels, allowing easy implementations of 360º camera views and image recognition, just an example of the possible driver assistance functions. OpenCV support for IMP-X4 will also be offered. The R-Car H2 offers the highest level of integration of advanced safety concepts and infotainment features in the automotive market today.

The highly efficient bus architecture of the R-Car H2 includes dedicated CPU and IP caches, enabling Renesas to reduce the DDR3 memory bandwidth consumption. In order to ensure adequate memory bandwidth, the R-Car H2 is equipped with two independent DDR3-1600 32-bit interfaces. This allows for much more efficient access to different content simultaneously, compared to a single 64-bit DDR interface.

Samples of the Renesas R-Car H2 SoC are available today, equipped in a 831-pin FCBGA (flip chip ball grid array) package. Mass production is scheduled for mid-2014.

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