CES: CEVA releases architecture enhancements for the CEVA-TeakLite-4 DSP
CEVA, Inc. has announced the CEVA-TeakLite-4 v2 DSP architecture with architectural enhancements that include new power optimization features to the instruction set architecture (ISA) and power scaling unit (PSU), facilitating even lower power consumption of up to 20%. For further die size optimizations, the latest architecture release enables a reduction in code size of up to 30% for key audio and voice codecs, significantly improving overall system cost.
Enhancements also include 50 new instructions, improved 64-bit data processing support, scalable data bandwidth up to 128-bit and a robust system interface that spans from low-power AHB bus to high-performance AXI bus with various master/slave configurations. The CEVA-TeakLite-4 v2 architecture framework is now deployed across the family of CEVA-TeakLite-4 cores, namely the CEVA-TL410, CEVA-TL411, CEVA-TL420 and CEVA-TL421.
To further assist customers with system integration of the CEVA-TeakLite-4 DSP cores in Android-based devices, CEVA is providing the AMF (Android Multimedia Framework), a proprietary framework enabling audio tasks to be seamlessly offloaded from CPU to the CEVA-TeakLite-4 DSP, allowing up to 8x in power savings. CEVA will demonstrate AMF running on an Android-based system at CES 2014 in Las Vegas, January 7-10th. To arrange a demonstration, please email firstname.lastname@example.org.
The CEVA-TeakLite-4 is the fourth generation DSP based on the CEVA-TeakLite architecture. The CEVA-TeakLite-4 is offered as a scalable and extensible architecture framework, allowing customers to choose the optimal family member core to address their specific audio/voice application needs. By taking advantage of a unified development infrastructure composed of code-compatible cores, a set of optimized software libraries and a unified tool chain, customers can significantly reduce software development costs while leveraging their software investment in future products.
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