Secure Boot Reference Design enables processors to boot securely in connected systems

February 11, 2014

Toni_McConnel-February 11, 2014

Microsemi Corporation is offering a new FPGA-based Secure Boot Reference Design for embedded microprocessors. This new reference design uses the advanced security features in its mainstream SmartFusion2 SoC FPGAs to securely boot any application processor in an embedded system, and ensures that processor code can be trusted during execution. This allows applications running on the securely booted processor to extend that trust to their system and to other connected systems.

Microsemi’s reference design is enabled by its SmartFusion2 SoC FPGA, which offers a number of advanced security features including on-chip oscillators, accelerators for cryptographic services, secure key storage, a true random number generator, on-chip boot code storage in secure embedded flash memory (eNVM) and at-speed serial peripheral interface (SPI) flash memory emulation to enable a secure boot of an external processor at speed. The devices also feature stronger design security than other FPGAs and include differential power analysis (DPA) resistant anti-tamper measures using technology licensed from Cryptography Research Incorporated (CRI).


The reference design also provides a public instance of Microsemi’s WhiteboxCRYPTO security product, which enables transport of a symmetric encryption key in a plain text environment through complex algebraic decomposition of the crypto key and strong obfuscation. A graphical user interface (GUI) device allows users to encrypt their application code for subsequent programing into an SPI flash and decryption in the host processor for execution. In addition, a complete user’s guide assists developers with implementing secure boot capabilities in their embedded systems.

When compared to other 5G SERDES-based FPGAs under 150K logic elements (LEs), SmartFusion2 devices’ high level of integration provides the lowest total system cost versus competitive FPGAs while improving reliability, significantly reducing power and systematically protecting customers’ valuable design IPs.

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