Polar enhances Si9000e transmission line field solverPolar Instruments has added enhanced modeling of both the drum and matte surfaces of copper layers in high-speed PCB stack-ups to the Si9000e PCB transmission line field solver.
Copper surface modeling adds an extra dimension to the accuracy of insertion-loss management across a range of frequencies, which is particularly important for the fabrication of multi-GHz PCBs.
The enhanced Si9000e system gives PCB fabricators the ability to provide advanced control of insertion losses and to combine lower material costs with higher manufacturing yields.
The matte surface of copper layers in PCBs is chemically treated to give greater adhesion to the dielectric layers in PCB stacks. At low frequencies, surface roughness has no affect on PCB performance because the current is able to penetrate below the surface of the copper layer.
However, in high-speed PCBs, a ‘skin effect’ causes most of the current to flow along the surface, following the rough contours of the copper and therefore increasing both the distance and resistance. The amount of attenuation is determined by a combination of the roughness of the matte copper surface and by the frequency of the PCB.
In addition to modeling transmission line losses on both the smooth and treated sides of the copper layers, and importing material Er and Tan delta over multiple frequencies, the Si9000e’s powerful boundary-element method (BEM) field solver models over 100 PCB transmission line structures.
The Si9000e can help designers to predict impedance, attenuation, RLGC, and s-parameters with frequencies ranging from a few kHz up to the point where the line ceases to operate in TEM mode, which is typically around 100GHz. The system allows users to explore ‘what if’ scenarios for rapid simulation of the impact of different materials and geometries.
By interfacing with Polar Speedstack layer stack-up system, Si9000e also allows designers to accurately document complex stackups in minutes.
The Si9000e can be used in pre-layout design, reference chipset stackup design and post-layout modeling of impedance and insertion loss by PCB fabricators.
Currently no items