ANAHEIM, Calif. — The Accellera standards organization is playing a crucial role in the development of SystemVerilog 3.1, according to language expert Stuart Sutherland, who spoke at a SystemVerilog workshop at the Design Automation Conference here Monday (June 2). Sutherland, principal at consulting firm Sutherland HDL, also outlined the process that Accellera went through to create SystemVerilog 3.1.

Accellera and the IEEE 1364 standards committee clashed on the eve of DAC, as the IEEE 1364 group called for technology donations for the next version of Verilog and set up a user's forum with no input from Accellera. "In light of the recent interest in the press, a lot of you are probably asking why Accellera is working on an IEEE standard," Sutherland said.

"I can offer my own opinion. There is no question that the IEEE governs the 1364 standard. But if you look at history, it took the IEEE five years to agree on the relatively minor changes between Verilog 1995 and Verilog 2001. The academic approach that the IEEE uses will simply take too long."

Sutherland described the Accellera process of starting with the existing Verilog 2001 and soliciting donations of concepts that could extend the language quickly. He said that Accellera's role was to seek appropriate donations and "munge them together" to form a standard that met the needs of designers.

The language guru described how Accellera had augmented Verilog with donated extensions in three specific areas: system modeling, verification, and borrowings from C/C++. In the first category, Sutherland cited SystemVerilog's Interface construct, which makes links between modules separate entities, independent of the modules and their ports and capable of containing their own protocols and assertions. He also pointed to the extension of the Port concept to allow any data type to be passed through ports.

In addition of assertions to the language, Sutherland said, the committee had decided against continued reliance on the Open Verification Library, which he described as valuable but, since it had to be implemented in Verilog, rather verbose and clumsy. The group also decided that a band-aid approach based on pragmas was inappropriate, since there was virtually no way to make it tool-independent.

In adding C-like constructs, Sutherland pointed to the additions of 2-state data types, enumerated and user-defined types, structures and unions, and a superset of the C-language operators. "You wouldn't believe how many times we've been asked just for the ++ operator," he remarked.

He also emphasized the importance of the new Direct Programming Interface (DPI) which permits C-language functions to be called directly from System Verilog, and SystemVerilog functions to be called directly from C. "I am a great fan of the existing Programming Language Interface (PLI,)" Sutherland said. "But it's complex, and not every application needs that much complexity. This is a much simpler way to create an interaction of SystemVerilog and C or SystemC code."

Sutherland briefly reviewed the considerations of the committee in keeping absolute backward compatibility with Verilog 2001, incorporating the work of others with as little modification as necessary, but still trying to maintain some degree of uniformity.

"Admittedly this has led to inconsistencies in syntax," Sutherland said. "For example, if you look at the extensions for verification, you will see constructs that look a lot like Vera." Another cost had been a large number of new keywords, he admitted.

But he defended these as the necessary price of promptness, pointing out that the Accellera board had voted to accept a completed SystemVerilog 3.1 standard on May 29. Sutherland contributed a SystemVerilog 3.1 tutorial to EEdesign in May.