San Jose, Calif. -- Sun Microsystems Inc. will pack native PCI Express and 10-Gbit Ethernet interfaces onto its next-generation Niagara processor, the company announced at the Hot Chips conference last week. The resulting server-on-a-chip--a first for the mainstream computer industry--generated debate about the future of integrated I/O in the era of multicore microprocessors.

Some saw Niagara-2 as marking the first step toward some day putting programmable serdes on a processor. That would effectively create a universal interconnect that could fundamentally reshape how computers are built. Others argued that I/O integration will likely play a more modest role in the future of computer CPUs.

Sun has been trying to carve out a leadership position in aggressive multicore designs with the Niagara chips, acquired from startup Afara Websystems, to break out of a market increasingly dominated by the X86. Thus, Niagara-2 packs eight cores, each running up to eight threads in parallel, as well as hardware acceleration for cryptography, two 10-Gbit Ethernet ports and eight lanes of PCI Express--far beyond anything proposed by Intel Corp. or Advanced Micro Devices Inc.

"I see a lot of upside with [PCI] Express integration. It's a stepwise refinement on the road to universal I/O," said Michael Krause, an interconnect specialist in Hewlett-Packard Co.'s X86 server group, which competes with Sun.

In Krause's long-term vision, on-chip serdes could be programmed on the fly to handle whatever interconnect protocol a system might require--Ethernet, Express or even storage links like serial ATA. That could reduce the need for discrete "south bridge" chips for I/O and potentially even eliminate expansion slots and cards.

The resulting systems would be highly simplified versions of today's servers, sporting a few CPUs linked by pc-board traces to various connectors and devices. In this scenario, the cost-squeezed computer industry would undergo another massive consolidation in which many of today's third-party chip and board makers would wither away, their features sucked into an Intel or AMD processor. "That's where the industry is going," Krause said. "It could really simplify things and it could fundamentally change system design."

It may take until 2010 for such CPUs to arrive, because they will need the process technology to support die sizes that afford adequate links to external memory. "The biggest challenge is memory bandwidth," said Krause.

Many observers see this vision as too extreme. I/O integration "sounds like a good idea at first blush, but when you start digging it's not such a good idea," said Chuck Moore, a chief architect at AMD.

Systems gain little because they probably will still need discrete I/O chips, and CPUs will take on a huge burden because they will need to be validated against a fast-changing world of interconnect protocols and third-party devices, Moore said. Also, I/O features don't need the aggressive process technologies used for CPUs, he argued. Thus, Niagara-2 makes sense for Sun, which is trying to create a unique position in high-performance, low-cost servers. But general-purpose server processors from AMD and Intel are not likely to follow suit, Moore said.

"Until customers really say they need [I/O integration], I don't see it happening," he concluded.

Ironically, AMD's parts already sport more I/O integration than those of its archrival, Intel. AMD recently announced that its next-generation Opteron chips for servers will have four, rather than three, HyperTransport interconnects on board.

AMD is also preparing to license its proprietary coherent version of HyperTransport. That move lays the groundwork for accelerator chips that directly attach to the Opteron. They could easily become cores sucked into future Opteron processors.