In "Coverage Driven Verification (CDV) for embedded software (ESC-463)," Andrews describes how some of the basic principles of hardware verification for automation, throughput and scalability can be applied to software verification. He uses a Linux device driver from a USB subsystem running a Linux kernel in a virtual machine hypervisor to show how device driver verification can be done using CDV.
In "A Methodology for successful VHDL"based FPGA design (ESC-462)," Weyand describes how to take methodologies commonly used in software design for structured code development, documentation and organization and apply them to VHDL-based FPGA design.
Synching up hardware and software
verification
In his course on coverage driven verification for software, Andrews -
an architect working in the areas of embedded software and hardware
verification for SoC designs at Cadence Design Systems - focuses most
of his attention on Linux device drivers, although such techniques can
be useful in many software environments, such as GUI testing and
library/API verification.
In Linux systems, he said, device drivers are normally tested by running them on the real hardware and observing the results. Some techniques exist to help with driver debugging but there are none that help much with dynamic verification. Most drivers are tested using some kind of system "stress test" that attempts to strain the system and the drivers to make sure they are stable under heavy load conditions.
"Although all of these and other tools and techniques are useful for testing drivers, there are no tools for verification planning, stimulus generation, functional coverage collection, and automated and coordinated stimulus for both the driver and the hardware it is controlling," said Andrews, and is an area where the basic principles used in hardware verification, as well as more advanced techniques for automation, throughput, and scalability, can be applied usefully.
. "In the past, many hardware verification users were primarily companies selling chips," he said. "Today, these same companies cannot compete in the market by providing a data sheet and device samples, but instead must develop chips, create evaluation platforms by putting chips on boards, and then provide all of the software to demonstrate a working system to prospective customers.
This has lead to increased investment in software by chip design companies and, as a result, over the last few years, Coverage Driven Verification has been working to fill this verification gap by enabling users to better utilize software as part of the hardware verification process in the familiar verification environments of Verilog, VHDL, and SystemC.
"In the future CDV will continue to focus on the chip customers who are developing software using many execution engines for simulation and emulation," he said. "There are also new opportunities for the application of Coverage Driven Verification technology in embedded software."
Structuring your FPGA design
process for success
In his class, Weyand " a principal systems engineer at Embedded Systems
Design, Inc. - describes how to use a well-defined and documented
VHDL-based FPGA design process that brakes up hardware development
process into seven phases - requirements definition, preliminary
design, detailed design, module level VHDL coding/simulation, top level
VHDL coding/simulation, synthesis, and implementation.
"In many hardware design organizations, the process for VHDL-based FPGA design is poorly defined and often undocumented," he said. "Individual designers tend to design FPGAs using their own methods that are often inconsistent with those methods used by other designers within the same organization. "
More often than not, FPGA designs are produced without the reviews necessary to ensure critical risks are mitigated and without the necessary documentation needed for integration and test. Managers and technical leads, he said, also suffer because they have little visibility into design progress and are unable to apply design resources efficiently.
"The negative effects of a poorly defined and undocumented VHDL-based FPGA design process are significant," said Weyand. "At the start of an FPGA design project, the design process cannot be efficiently tailored to eliminate unnecessary steps and emphasize others. This often results in time wasted on unnecessary steps and increased risk because more important steps aren't given enough attention. "
After the FPGA design effort starts, serious design issues are often discovered late in the design cycle when design changes have a substantial cost and schedule impact. FPGA designs may not fit in the targeted package, not meet the required timing, or consume too much power.
The resolution of these issues, said Weyand, usually requires the repetition of FPGA design process steps and sometimes even modifications to board designs or system requirements. "When the FPGA design is completed, the resulting documentation available for integration and test is often limited and inconsistent," he said. "In many cases the only useful FPGA documentation is comments provided within the VHDL code. Other designers using the design are often forced to 'reverse-engineer' the FPGA functionality from the VHDL code."
In addition to negative impacts to the current FPGA design, Wyand said the lack of a structured design prevents the efficient reuse of common VHDL modules by other FPGA designers. Common, reusable modules are not identified and documented properly and so cannot be ported to other designs. Also, the lack of well-defined process phases leaves engineers and managers with no useful basis of estimation for future FPGA design efforts.
He said there are several benefits of the well-defined and documented VHDL-based FPGA design process desribed in his class. "First, the process may be tailored to emphasize some phases and deemphasize others resulting in increased efficiency and reduced risk," he said. "Second, it is well structured and includes design reviews that force FPGA design issues to be discovered and addressed early in the design cycle when the impact of design changes is minimized. Third, it provides complete, accurate design documentation for FPGA integration and test."
This VHDL-based FPGA design process also benefits future FPGA design efforts within an organization. "Common, reusable VHDL modules are identified and documented so they may be easily ported to other FPGA designs," said Weyand. "Also, the well-defined and clearly delineated process phases allow current design efforts to provide a useful basis of estimation for future FPGA design efforts. Finally, less experienced FPGA designers are given a proven and well-documented roadmap to follow."
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