Researchers from Nanoelectronic Devices Laboratory of the Swiss Federal Institute of Technology Lausanne are set to report on progress on two fundamental energy-efficient devices at the 2008 IEEE International Electron Devices Meeting (IEDM), due to run in San Francisco, Dec. 15 to 17.
The second paper concerns the experimental demonstration of a ferroelectric abrupt electronic switch with a sub-threshold swing better than the limit of 60mV-per-decade of MOSFET at room temperature. This minimum sub-threshold swing in conventional MOS transistors puts a fundamental lower limit on the operating voltage and the power dissipation of standards FETs.
The authors report sub-threshold swings as low as 13mV-per-decade in ferroelectric FETs with made with a 40-nm poly vinylidene fluoride trifluoroethylene (P(VDF-TrFE))over silicon dioxide gate stack.
The P(VDF-TrFE) is a dielectric layer on the top of silicon oxide with a 100-nm gold layer as the metal contact on top of this gate stack. The FET channel is silicon (n-channel enhancement-mode MOSFET).
There are many reasons for using PVDF: has a large spontaneous polarization, very good polarization stability, very low leakage due to the high resistivity. But on top of that does not require high-temperature processing (sub-200°C), is low cost and very stable, which makes it compatible with CMOS. Moreover, this creates the possibility of using it in the future for abrupt switches or non-volatile memories on flexible substrates (not only on silicon).
The mechanism governing the low subthreshold swing in Fe-FET transistors is the negative capacitance of the ferroelectric layer that can provide voltage amplification.
