San Francisco — Forte Design Systems will roll out an upgraded version of its Cynthesizer SystemC-based behavioral-synthesis tool this week. Forte introduced Cynthesizer last year, touting it as both a step toward enabling broader adoption of electronic system-level design and a second chance for behavioral synthesis.

Version 2.5 comes with new capabilities that are said to further ease the adoption of higher-level design. It adds support for power estimation, formal verification, modular interface intellectual property (IP), FPGA prototyping and a new design-reporting subsystem.

The company has enhanced the flow, adding "improved analysis capabilities and improving the results that you can get at the back end," said Brett Cline, vice president of customer operations and services at Forte (San Jose, Calif.).

Support for power optimization comes through collaboration with Sequence Design Inc. (Santa Clara, Calif.). Mutual customers now have the ability to automatically measure power consumption at the register-transfer and gate levels using Sequence's PowerTheater product. According to Forte, measuring power throughout the SystemC-to-netlist design process, and reporting power estimates along with area and timing, enable users to engage in design trade-offs for cost, performance and power.

Cynthesizer now supports RTL-to-gates formal verification with the Encounter Conformal equivalence checker product from Cadence Design Systems Inc., an enhancement that Forte says will enable users to formally verify the optimized RTL created by Cynthesizer with their postlogic synthesis netlist results.

Support for FPGA implementation targets eliminates the need to create several RTL design versions for multiple devices, said Forte. Cynthesizer 2.5 users can prototype their designs as FPGAs through a link to Synplicity Inc.'s Synplify Pro tool.

Forte continues to see Cynthesizer mainly as a system-on-chip and ASIC design tool, Cline said. But, he added, "FPGAs are a real part of this world."

Easy IP reuse
The latest release also enables design teams to incorporate modular and configurable interfaces with their C, C++ and SystemC design models and, ultimately, create reusable interface IP. According to Forte, Cynthesizer automatically produces an RTL hardware description with an optimal schedule and resource utilization for the interface protocol being targeted. This lets designers analyze different scenarios, while saving silicon space by eliminating the need for independent layers. This enhancement "is going to give people the capability to reuse their IP a lot more easily," Cline said.

Cynthesizer 2.5 has several new analysis capabilities, including direct links from RTL hardware to the original C, C++

and SystemC code, and detailed cycle-by-cycle resource-scheduling information. An HTML-based analysis subsystem allows designers to easily analyze their design, evaluate trade-offs and achieve rapid closure, the company said.