Venice, Florida — Ciranova, Inc. has released Ciranova Helix, an automated analog layout solution that optimizes both circuit and device layout simultaneously. For an analog layout automation tool to deliver production-ready results, it must simultaneously optimize circuit design requirements (matching, symmetry) with device layout requirements (device and contact ring abutment, well merging), while always obeying process requirements (design and DFM rules).

Ciranova Helix fast run times enable designers to explore multiple layout alternatives and extract parasitics early in the design process. Ciranova Helix benchmark results include placement of a 154 transistor PLL circuit in under 4 minutes on an N processor Linux server.

The tool's primary inputs are a SPICE netlist and a Process Design Kit (PDK) containing either Cadence SKILL PCells or Ciranova PyCells, such as those in the Interoperable PCell Library (Interoperable p-cell library launched). Designers may also specify symmetry, device matching, and other high-level circuit intent, which are obeyed by the tool no matter which PCells and process technology are used. The output is full device-level placement, DRC-correct, in either OpenAccess or GDS format.

Helix is a native OpenAccess tool, and integrates seamlessly with Cadence Virtuoso, Silicon Canvas Laker, and Magma Titan, as well as DRC tools such as Mentor Graphics Calibre and Synopsys Hercules.

Ciranova Helix is available now. Foundry processes from 250nm to 40nm are currently supported with more under development. Ciranova Helix is currently supported on 32-bit and 64-bit Linux, Solaris 8 and Solaris 10 and Microsoft Windows. For pricing information, contact Ciranova.