CoWare announced the availability of a new interconnect and memory-subsystem performance optimization design flow for its Platform Architect product. This enables early and efficient optimization of next-generation system-on-chip (SoC) architectures using ARM AMBA-based virtual platforms. Virtual platforms for architecture design are the virtualized representation of an electronic system used for the purpose of system-level performance analysis and architecture optimization. The new flow gives system architects the ability to efficiently capture the dynamic performance workloads of each application subsystem of a multi-function SoC in the form of transaction traffic, months before software is available and with minimum modeling effort using a well-defined, repeatable methodology.

The design flow for is enabled by the company's advanced system-level design features, including trace- and task-driven generation of transaction traffic, enabling creation of performance workload models reflecting the application performance workloads of the multi-function use-cases for interconnect and memory subsystem analysis; and an integrated graphical environment for transaction tracing and statistical port analysis enabling platform model validation and system-level performance measurement of transaction count, transaction throughput, and transaction latency.

Other features include support for simulation and analysis of multiple TLM protocols at mixed levels of abstraction, including TLM-2.0 and cycle-accurate AHB, APB, and AXI communication protocols, and user-defined data collection based on SCV transaction recording; and scripting support for simulation sweeping of traffic scenarios and IP parameters across multiple simulations enabling design space exploration, sensitivity analysis using spreadsheets, and root cause analysis;

The CoWare Platform Architect tool and IP model enhancements and CoWare CoStart services are available immediately for use with the 2009.1.1 release. For more information, visit www.coware.com.