Development support is now available for the ST100 DSP core architecture. This support takes the form of an integrated software toolset and a development board that allow users to prototype system-on-chip products using the dual-MAC ST120 core, the first implementation of the ST100 architecture. ST100 family cores offer a 32-bit superscalar architecture with three software-selectable instruction modes (16-bit, 32-bit, and 128-bit instruction words) that can be combined in the same application. The ST120 core has a dual-data unit and dual-address unit parallel architecture that can execute up to four 32-bit instructions in a single cycle using the 128-bit score boarded long instruction word operation, and supports single instruction multiple data (SIMD) mode. Intended for evaluation and early-prototyping of ST120-based system-on-chip products, the ST120-EVA chip integrates the ST120 core with 128KB of program memory and 32Kwords data memory, a 32-line interrupt controller, two timers, two serial I/O interfaces, a 16-bit GPIO, a host port interface, and an external memory interface. Debug support is provided through an on-chip emulator module communicating with the ST120 debuggin suite through a standard JTAG interface.
STMicroelectronics
Lexington, MA
(781) 861-2650
www.st.com
Return to April ESP Index
