The SR71000 is an embedded MIPS processor with speed grades up to 800MHz. The processor is an implementation of the MIPS64 instruction set architecture that incorporates a multi-pipelined design with dynamic branch prediction and low power consumption. At the heart of the processor is a single MIPS64 CPU core. The processor can issue and execute up to six instructions per clock cycle. The architecture incorporates dual instruction fetch, dual dispatch, and dual commit. The SR71000 includes integrated on-chip memory, including 32KB each of primary instruction and primary data cache; 512KB of unified secondary cache; and tertiary cache control. The 64-bit system interface is compatible with existing implementations of the MIPS address and data interface, operating at an interface bus frequency of up to 133MHz. The SR71000 support toolkit includes a set of simulation tools and development boards with Ethernet ports and logic analyzer connection ports. The 600MHz and 500MHz versions are sampling now, and the 800MHz speed grade will sample in the first quarter of 2002.

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