MIPS Technologies has enhanced its MIPS32 and MIPS64 RISC microprocessor architectures by reducing interrupt latency, adding vectored interrupts, and allowing the architectures to manipulate bits within data packets and device registers. These enhancements allow MIPS64-compliant coprocessors, such as floating-point units, to be combined with a 32-bit CPU. The new architectures will support all legacy IP and will be compatible with third-party tools, operating systems, and application software supporting the MIPS architecture. They are available for licensing now.

MIPS Technologies
Mountain View, CA
(650) 567-5000
www.mips.com