Nios 2.1 is an updated general purpose RISC processor for Altera CPLDs. It features a 16-bit instruction set and user-selectable 16- or 32-bit data paths, configurable for a range of applications. Version 2.1 takes advantage of Stratix's TriMatrix on-chip memory, high-performance interconnects, and embedded digital signal processing blocks. Nios users can optimize their system data flow using the simultaneous multi-master Avalon bus and custom instructions. Nios 2.1 includes the SOPC Builder development tools 2.52. SOPC Builder generates hardware description language (HDL) that is tailored to specific device families. Quartus II 2.0 development software is included with Nios 2.1. Nios 2.1 is available now.

Altera
San Jose, CA
(858) 202-3700
www.altera.com