Austin, Texas — The RapidIO Trade Association has released full details of its serial chip- and board-level interconnect specification. Combined with the trade association's parallel specification completed last year, full availability of Serial RapidIO allows designers to standardize on a single interconnect technology for networking, telecommunications and other embedded applications.

Details of the technology have been available to members of the association since January of this year. First products based on the specification are expected to be available in early 2003.

Serial RapidIO is a high-performance, low pin-count, switch fabric serial interconnect for applications such as DSP farms and newly emerging serial back plane applications.

The congruency between the two specifications is important because semiconductor and ASIC developers bringing serial chips to market can reuse much of their original RapidIO parallel design. Serial RapidIO preserves the upper layer specifications, protecting vendors' original investment in RapidIO design and verification.

Serial RapidIO is based on industry-standard signaling technology found in Fibre Channel, 10Gbit Ethernet XAUI interfaces and Infiniband, and includes a low-power transmission mode not found in other standards. It operates at 1.25, 2.5 and 3.125 Gbit/s, providing the required bandwidth for signal processors and back plane applications.

The specification defines both a single differential link in each direction between devices and support for ganging four links together for higher throughput applications. On the system level, designers can connect parallel and serial RapidIO devices through switches without using special bridging functions.

The specification can be downloaded from the association's web site at http://www.RapidIO.org .