Naman Gupta

Design Engineer

Naman Gupta received his B.E. degree in Electronics and Communication from Netaji Subhas Institute of Technology, Delhi University in the year 2011. He is currently working as a Design Engineer with Freescale Semiconductor, Noida, India. His primary responsibilities include timing closure and constraints development. His research interests include high speed, low power and programmable design architectures. He can be contacted via email at naman (dot) gupta (at) freescale (dot) com

Naman Gupta

's contributions
    • Hi Pritkiy, One can add extra FF as long as the desired functionality of the circuit remains the same. But having said that, one cannot deny the benefits of using clock gating cells to save dynamic power. In modern complex designs with stringent power budgets, gating the clock is an indispensable design solution. With proper understanding of the design intent, and the timing requirements of the clock-gating checks, I don't see any reason why should designers be wary of gating the clocks.

    • Hi Acasprado, I believe by clock enable you mean using a multiplexer with it's select line as the clock enable? If yes, one could definitely use this. However, this approach does not result in any overall dynamic power savings because the flip-flops at the output of the multiplexer still continue to receive the clock at all times.