aspenlogic

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    • I too have rescued numerous projects in the FPGA logic space. My conclusions are a little different then yours however. I see three problem themes: 1) Reset design is a topic given little up front thought but tends to accumulate insidious, hard to find bugs, 2) Management assigns a cost of $0 to bugs because FPGA devices are re-programmable so design and verification have no value, and 3) projects lack roadmaps. To understand how I believe these contribute to failures visit https://aspenlogic.com/blahblahblog/2017/02/24/bugs-not-in-my-schedule-please/