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  • IC Design: Preparing for the Next Node

    Although rarely discussed, the EDA industry is also constantly in a state of preparing for the next node. All those new process technologies and new design functionality add up to an ever-increasing pressure for increased automation in verification using a set of foundry-qualified tools, all while maintaining the highest level of accuracy without driving up runtimes. Read this paper to learn more.Read More

    Which DDR SDRAM Memory to Use and When

    This white paper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.Read More

    Plastic Electrical Enclosures: Solutions for Extreme Customization

    Now, more than ever, standard, off-the-shelf, plastic enclosures offer cost-effective value for customized electronics packaging. Read this paper to learn more.Read More

    The Value of Using a Unified C/C++ Testing Tool

    This paper discusses the benefits of implementing a unified testing tool to optimize multiple automated testing technologies including code coverage, unit testing, static analysis, and runtime analysis.Read More

    Accelerating MISRA C and SEI CERT C Compliance

    This paper discusses what it really means to achieve coding standard compliance, using MISRA C 2012 and SEI CERT C as examples, and how to accelerate compliance with tool automation, dedicated reporting, and workflow management, drastically reducing the manual effort required.Read More

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IC Design: Preparing for the Next Node

Save & Follow 01 March 2019

Although rarely discussed,... Read More

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stephan.zorn many thanks ! (Read More)
misterb Thanks Dan! great article, I enjoy reading... (Read More)
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