Fault diagnosis of onboard automobile machine control using FFT algorithms
Fast Fourier Transform. Once filtered, the signal is fed to the
FFT engine to transform the signal into the frequency domain. The signal
is then added to the previously obtained FFT vector to average it out
for noise cancellation. This process is done a number of times, and
depends entirely on the signal-to-noise ratio. Once the signal has been
averaged a particular number of times, a simple loop is required to
detect a peak in the frequency spectrum that is higher than the
threshold. This detects the presence of high frequency components.
The developed system is primarily focused on fault detection of an automobile starter motor. The maximum speed can go up to 2500 RPM; normally the speed remains within 1400~1500 rpm, or 25 revolutions per second. This means that complete information about the gear can be acquired within 40ms. During this period (with a sampling frequency of 10kHz), the number of acquired data points will be only 400. The sampling rate of our ADC is tuned to 10,000 samples per second. Since we only need 400 samples to model our frequency domain behavior, this sharply decreases our time sample space, something which is essential to performing and storing the FFT, given the limited on-chip memory of embedded devices.
To minimize cost while maximizing performance, we set benchmarks against different devices, and judged them on a variety of variables including clock speed, memory, and hardware-optimized components. In particular, we compared a digital signal processor (DSP), FPGA, and Cypress’ Programmable System on Chip (PSoC) devices. Concretely, our primary concerns with any device were cost, FFT benchmarks, pre-filtering, and memory.
FFT Benchmarks. As mentioned above, our sample space is a frame of 512 points in a 16-bit unsigned integer format. Each of these samples is stored in the Q8.8 format, where the first 8 bits are for the integer part, and the last 8 bits are used for the fractional part. We implemented the 512-point FFT transform in C. The twiddle factors for the computation were stored in the Flash to save on SRAM.
DSP versus PSoC algorithm implementation
In our evaluation the PSoC family of devices exceeded the DSP architecture because of parallelization and onboard peripherals. For example, most DSPs feature no ADC, nor can they filter the signal at the same time as computing the FFT since it is a single-core device. In contrast, the PSoC can accumulate filter results while simultaneously processing the FFT on the previously stored samples. This is possible because the filter is implemented in a mini DSP that is independent of the main core. The filter can then transfer results directly into memory using DMA and later loaded into the FFT input space.
Additional wiring costs
The addition of an external ADC entails cost as well as wiring needs. Since PSoC integrates the required peripherals available in a single chip, no external components for processing data are required.
The current samples are obtained by coupling the ADC with a shunt resistor. The width of current samples is 8 bits each. Once 512 samples have been obtained, the FFT routine is run to transform the time domain signal into the frequency domain.
The current source is sampled by a Delta Sigma ADC embedded in the PSoC machine. This is a high quality analog-to-digital converter with the added capabilitiy of multi-sampling, i.e., the same ADC can be switched to different sampling rates with different bit widths. This supports different scenarios where we may have to deal with multiple motors with dramatically different requirements.
While this method is significantly powerful, this model for fault detection in electrical machines has significant problems when it comes to dealing with transients that are in the form of very sharp receding impulses, since the FFT fails to identify sharp vanishing impulses in the frequency spectrum. A loss of information occurs at this stage, which can create significant hurdles in designing a system that can identify faults in electrical machines.
This problem can be addressed by employing a Wavelet Transform, an efficient technique to resolve time domain signals into the time-frequency spectrum while preserving information related to sharp impulses as well as high frequency harmonics.
By carefully designing features and using machine learning methods, significant improvements can be made in fault diagnostics in electrical machines. Another trend that has recently emerged is the use of graphical systems for fault diagnostics and prognosis, first reported by Zaidi et el , who used Hidden Markov Models for this purpose. These models provide a significant challenge in their porting to embedded systems because of extensive usage of computational resources.
1. “A Micropower Support Vector Machine Based Seizure Detection Architecture for Embedded Medical Device”s by Ali Shoeb, Dave Carlson, Eric Panken Timothy Denison. Published in the Proceedings of 31st Annual International Conference of the IEEE EMBS, Minneapolis, Minnesota, USA, September 2-6. 2009
2. “Fault Diagnosis and Failure Diagnosis for Electrical Machines” By Syed Sajjad Haider Zaidi – Dissertation submitted to Michigan State University - 2010
Salman Javaid is a graduate student in Electrical Engineering at the National University of Science and Technology, Pakistan. He has been working with Cypress' Programmable System on Chip design for the last year. His current research involves designing robust and accurate embedded designs for fault diagnostics in electrical machines using Cypress' PSoC.
Syed Sajjad H Zaidi is the Head of Electronics and Power Engineering Laboratories in the Pakistan Navy Engineering College (PNEC, Karachi), National University of Sciences and Technology (NUST), Pakistan. He has a doctorate degree from Michigan State University in the electrical machines fault diagnosis and prognosis using non-intrusive methods. He specializes in Electrical Machines, Signal Processing, Pattern Recognition and Time Frequency transformation. His research interests in the areas of condition-based maintenance, fault prediction and estimation, system engineering and designing.
Ahmed Majeed Khan is an engineer experienced in working with cross-functional groups to push the envelope of technology implemented in electronic products. Mr. Khan is from a consumer electronics background and his expertise includes embedded systems and wireless multimedia communication. He personally developed and led teams to develop several high volume, high quality products. Currently, Mr. Khan is an engineer at Cypress Semiconductor Corporation, where he developed and assisted the development of multiple programmable solutions. He also established CY-SEECS Joint Research Center at National University of Sciences and Technology (NUST) in Islamabad, Pakistan. Mr. Khan holds an MS in Electrical Engineering from Michigan State University and has over 8 years of experience working with microcontrollers and embedded applications.