MoSys Unveils Its 1T-SRAM “CLASSIC Macro'' Family; Available on TSMC, Chartered, and SMIC 0.13micron Processes
Sunnyvale, Calif.MoSys, Inc., the industry's leading provider of high-density system-on-chip (SoC) embedded memory solutions announced today the availability of 1T-SRAM(R) “CLASSIC Memory Macros” – a family of pre-configured, high density, high speed, low power memory macros using silicon-proven 0.13 micron cores. By offering this set of macros in addition to its custom-designed embedded memory products, MoSys' customers now have the advantage of off-the-shelf, silicon-proven 1T-SRAM memory for rapid integration of high-density embedded memory into their SoC designs.
MoSys' CLASSIC Macros are available in both high speed and low power configurations, targeted at applications including performance computing, high-throughput data networking, portable mass storage as well as high volume consumer entertainment and wireless personal communications. High speed CLASSIC macros are available in 1 Megabit configurations with 32bit, 64bit or 128bit bus widths. Speeds of up to 266 MHz are supported. The low-power CLASSIC macros are available in 1Megabit, 2Megabit or 4 Megabit configurations, all with 32-bit bus widths. The low power offerings can operate at frequencies up to 133 MHz and feature standby power of less than 80 micro Amps per Megabit. All CLASSIC macros employ MoSys' patented TEC(R) technology resulting in higher yields, greater reliability and lower soft-error rates.
“Since its introduction, MoSys' 1T-SRAM technology has enabled designers to achieve significant performance advantages and cost savings,” said Karen Lamar, vice president of sales and marketing at MoSys. “By taking advantage of MoSys' pre-configured CLASSIC macro offerings, our customers now enjoy shorter design cycles and reduced development costs, while still retaining all of the performance benefits they have come to expect when using MoSys' technology.”
MoSys' CLASSIC macros are licensed on single project use basis, while allowing customers to use multiple instances in their designs to achieve larger on-chip memory sizes. CLASSIC macros are targeted for use with multiple foundries including Chartered, SMIC and TSMC, initially on the 0.13-micron process node. CLASSIC macro deliverables include datasheets, simulation and timing models, layout phantoms, GDSII databases and test documentation.
“With the new CLASSIC macros line, MoSys is offering its customers immediate access to the best combination of high-density, configurable bandwidth and low power in an embedded SRAM memory solution. Through use of its proprietary 1T-Q (single transistor, quad density) bit cell instantiated in CLASSIC pre-configured macros, MoSys delivers truly compelling embedded SRAM memory solutions for immediate use as a drop-in replacement for larger, less-power optimized embedded SRAMs. With CLASSIC macros onboard their consumer and communications SoCs, MoSys' customers greatly accelerate their time to market while saving engineering development costs, particularly for SoC designs with increasingly aggressive market windows,” said Rich Wawrzyniak, senior ASICs & SoC analyst with Semico Research. “MoSys' CLASSIC macros family greatly benefits fabless companies that do not have the capital resources or longer SoC design windows required to invest in a fully customizable 1T-SRAM solution. CLASSIC macros enable MoSys' customers to get the best bang for their buck by getting to market faster with optimal performance and significant cost savings.”
For customers with embedded memory requirements outside the scope of the CLASSIC macros, including projects in advanced deep sub-micron processes such as 90 nanometers, MoSys continues to provide its customized embedded 1T-SRAM memory macros.
Price and Availability MoSys 0.13-micron 1T-SRAM CLASSIC macros are available now with pricing on request. Silicon characterization reports will be available by September 2005.
ABOUT MOSYS Founded in 1991, MoSys (NASDAQ: MOSY), develops, licenses and markets innovative memory technologies for semiconductors. MoSys' patented 1T-SRAM technologies offer a combination of high density, low power consumption, high speed and low cost unmatched by other available memory technologies. The single transistor bit cell used in 1T-SRAM memory results in the technology achieving much higher density than traditional four or six transistor SRAMs while using the same standard logic manufacturing processes. 1T-SRAM technologies also offer the familiar, refresh-free interface and high performance for random address access cycles associated with traditional SRAMs. In addition, these technologies can reduce operating power consumption by a factor of four compared with traditional SRAM technology, contributing to making them ideal for embedding large memories in System on Chip (SoC) designs. MoSys' licensees have shipped more than 80 million chips incorporating 1T-SRAM embedded memory technologies, demonstrating excellent manufacturability in a wide range of silicon processes and applications. MoSys is headquartered at 1020 Stewart Drive, Sunnyvale, California 94085. More information is available on MoSys' website at http://www.mosys.com. The pioneers of single transistor (1T)-SRAM technology are at it again with an off-the-shelf solution that will cut SoC design time by at least two months. MoSys has developed a family of pre-configured memory macros called CLASSIC, which takes on the characteristics of its flagship customized embedded 1-T SRAM technology.
MoSys is targeting CLASSIC at two segments of the marketlow-power handheld consumer devices and high-speed, high-bandwidth applications, such as routers, switches and other types of networking applications.
“These will be silicon-proven, pre-configured memory blocks,” said Karen Lamar, vice president of sales and marketing at MoSys. “For a custom macro, the turnaround time for us to implement is typically on the order of 12 weeks. For a CLASSIC macro, the turnaround time is about two weeks. We address a wide variety of customer needs. We have system-level designers, ASIC companies and the foundries.”
CLASSIC memory macros can be coupled with a new compiler from MoSys that will allow customers on the front-end to see how alterations and some of the parameters of the CLASSIC macro might affect their design. The compiler, which is electrically tuned and parametrically aligned with the CLASSIC macros, targets processes from several foundries, including Chartered, SMIC, TSMC and UMC.
“Customers have the flexibility to change the parameters on the CLASSIC macro and test drive it to see how it would work based on their requirements,” Lamar said.
In a 'class' of its own
The CLASSIC memory macro program is based on MoSys' 1-T SRAM-Q (quad-density) technology. When the company moved to 0.13-micron, it employed single trench isolation (STI) to produce a denser, more compact solution than its previous devices based on planar bit cell technology and competitors' 6-T SRAM products.
“We will continue to proliferate our Q-bit cell architecture and we will also work with our tech partners, like TSMC and Chartered, on other bit cell offerings,” Lamar said. “MoSys' 1-T SRAM technology will be in encased in the Q-bit cell going forward as well as MIM (metal-in-metal) at 90-nm that is offered at TSMC and NEC.”
The 1T-SRAM-Q architecture uses a folded area capacitor (FAC) to produce a very dense structure. The FAC reduces bit cell size by folding the bit cell gate oxide capacitor vertically down the STI sidewall, which reduces the horizontal area. This results in typical bit cell sizes of 0.57 square microns at the 0.13-micron process node.
“What that means in terms of operation is that it's faster and it's lower power than a 6-T implementation,” Lamar said.
It also features hidden refresh management circuitry, Lamar added. “When you talk about embedded memory, refresh is key. No external refresh is required for this.”
1T-SRAM-Q technology also incorporates MoSys' Transparent Error Correction (TEC) technology, which is embedded ECC circuitry at no additional cost. Competitive solutions require an external ECC implementation. With TEC, there is no additional silicon area required for the customer, Lamar said.
“The soft error susceptibility is very low with MoSys compared with high soft-error susceptibility with a 6-T solutions,” Lamar said, adding that the failures in time for its 1-T SRAM-Q technology is only 10 at 200-MHz.And since there is only a single transistor compared with six in a 6-T implementation, the macro is 70% smaller.
“There's a 1:1 correlation between size and cost. Foundries charge based on the area taken up in the die. From a customer perspective, they're better off with a denser solution. If the design is bigger, that means fewer can fit on a wafer,” Lamar said. As a result, the 1-T SRAM-Q solution costs less.
High speed or low-power
MoSys' low-power 1T-SRAM CLASSIC macro products come in three densities, including 1-Mbit, 2-Mbit and 4-Mbit; they are all a X32 configuration. The 1T-SRAM CLASSIC macro low-power products feature 20 to 133-MHz of operation, MoSys' standard SRAM interface, and flow-through read timing.
“A key feature here is our low active power at .25-miiliamps/per megahertz at continuous operation, which is important relative to the power. When we're offering how much power we're consuming, and its .25-milliamps/per megahertz, which is exceptionally low. It's at least 50% lower than 6T-SRAM,” Lamar said.
The low-power products also have an ultra-low retentive standby power of 80-microAmps per Mbit.
Where bandwidth is the issue, the 1-T SRAM CLASSIC macros have configurable bandwidths of X32, X64, or X128 and are 1-Mbit implementations. They feature 20 to 266-MHz of operation and MoSys' standard SRAM interface.
“The key here is its ability to retain low-active power, even though we're operating at high-speed, Lamar said. “It has pipelined read timing and .3-millamps /per megahertz at continuous operation. Here's its about 66% better than 6T SRAM devices.”
Both the low power and high-speed macros have early and late byte-write options. “This is where we feature ECC as well. 1-T SRAM solutions feature it and so do our compiler products,” Lamar said.
More on the compiler
The memory compiler is a web-accessible tool automatically generating a variety of design scenarios for MoSys' 1T-SRAM memory. It allows engineers to include 1T-SRAM macro instances in their layout by providing place and route view and design specifications, including memory size and configuration (number of words and word size), power and operating parameters, such as speed and temperature range. Based on this information, all the views needed for simulation, synthesis, floor-planning and place and route of their design are generated.
When high-speed macro options are specified, the compiler can produce macros capable of running up to 266-MHz with bus widths from 32 bits up to 256 bits wide.
Pricing and availability
The 0.13-micron, 1-T SRAM CLASSIC macros are available now with license fees starting at $200,000. Delivery time is two to four weeks. Silicon characterization reports will be available by July 2005. The compiler front-view generator is available now.
The compiler back-end optimizer is scheduled for release in October 2005.
MoSys Inc., 1-408-731-1800 www.mosys.com