16-bit RISC processor core combines low gate count, low power, and high code density - Embedded.com

16-bit RISC processor core combines low gate count, low power, and high code density

Cambridge Consultants released a 16-bit RISC processor IP core that offers a low gate count, low power consumption, and high code density. It's is optimized for use in cost and performance sensitive ASIC designs and is available for evaluation now. On a 0.18-micron CMOS fabrication process, the XAP4 can deliver up to 63 Dhrystone MIPS at a 117-MHz clock frequency.

The XAP4 has both 16-bit data and address buses and can run programs up to 64 kbytes. The first implementation of the processor has a two-stage pipelined Von Neumann architecture. It's delivered to licensees as a soft IP core in Verilog RTL that can be synthesized in as few as 12,000 gates.

The goal of the XAP4 is to fulfill the requirements of modern ASIC-based systems running code written by different programmers, including real-time operating systems. The processor includes hardware support for privileged OS modes where code running in user mode can't corrupt supervisor or interrupt code. Code is position independent and there's also support for unaligned data access, making programs easy to port and quick to run. There is hardware support for rapid context switching, for example, when interrupts occur, and there are multi-cycle instructions to speed up multiply, divide and block copy operations.

Other features include hardware support for operation as a slave processor when a master processor downloads a code image and bootstraps the XAP, and support for multi-processor debug. Details of the cores can be found at www.CambridgeConsultants.com/ASIC, including trial downloads of the xIDE software tools.

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