San Jose, Calif. — Renesas Technology Corp. has developed a newtechnique for increasing the speed of its digital signal processors and has applied it in a VLIW-type low-power-consumption synthesizable DSP core. The new core operates at 1GHz and can be embedded in SoC devices. Details of the DSP core were revealed in a technical paper presented atthe 2006 Symposium on VLSI Circuits held in Honolulu, Hawaii.
Test chips for the new Very Long Instruction Word (VLIW)-type synthesizable DSP core were fabricated using a 90nm CMOS process. The core achieved a maximum operating frequency of 1.047GHz at a supply voltage of 1.2 V. Power consumption for performing a 128-tap FIR filter operation at that speed was only 0.10mW/MHz, and the silicon area of the core was extremely compact: about 0.5mm2.
The DSP core uses a new saturation processing method with a saturation anticipator circuit, as well as a layout technique that implements a hierarchical structure optimized for operation speed. These features enable the core to achieve speeds that are approximately 20% faster than the previous Renesas DSP design.
According to Renesas, the quality and resolution of multimedia data such asaudio and video has increased, and the trend is continuing. This makesit necessary to process large volumes of multimedia data at extremelyhigh speed. For example, using the AAC (Advanced Audio Coding)compression format for audio data and a processing speed 12 times thenormal rate, it is possible to encode (convert to compressed form) onehour of audio data in five minutes. Thus, the audio content can berecorded in a small amount of time. Video contains much more data, however, and high-definition TV (HDTV) video is more data-intensive than standard TV (SDTV) video. For the H.264/AVC (Advanced Video Coding)video-compression format used in HDTV applications, for instance, theencoding workload imposed by the HDTV screen size (1,920 x 1,080 pixels)is six times that of SDTV screen size (720 x 480 pixels).
DSPs perform a large number of multiply-and-accumulate loop operations.They use guard bits to prevent overflows during arithmetic operationsand provide efficient data processing. If an overflow occurs when theDSP is converting data with a guard bit to data with no guard bit, thedata is converted to a specified maximum or minimum value. The saturation circuit performs the important function of detecting overflows.
saturation processing method
In contrast, the newly developed technique operates as follows: At the same time that the data is being input to the adder, the checker circuit uses leading-zero anticipation (LZA) to anticipate whether or not saturation will occur. Anticipation takes place in parallel with addition. Based on the anticipated result, the Anticipator circuit instructs the final stage of the arithmetic circuit to output either the result produced by the adder or the specified maximum or minimum value. The fact that the adder and Saturation Anticipator circuit operate in parallel increases the processing speed. This technique provides a speed boost of 10.5% over conventional designs.
Renesas also employs a Layout Technique with hierarchical structure optimized for operation speed. Conventional layouts have a hierarchical structure organized around the function modules. This results in “critical paths” for which speed becomes problematic as the wiring length gets longer. When developingthe new DSP, Renesas Technology analyzed the critical paths for whichspeed is most important, then created a hierarchical structure that isoptimized for operation speed. The optimization was aimed at shorteningthe wiring lengths of the critical paths. Critical paths are not routed via multiple modules. The arithmetic unit and bypass circuits such as the control lines connected to it, are bundled into a single module. Simulations show that the optimized structure achieves a speed increase of 9.3% over conventional designs.
Renesas Technology , (408) 382-7407
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