3-D ICs stack up design challenges - Embedded.com

3-D ICs stack up design challenges

In an address to the GlobalPress Forum in Santa Cruz on March 29, Mentor Graphics Chairman and CEO Walden Rhines (See picture ) outlined the likely evolutionary stages of 3-D IC development, from today's relatively simple stacked dice to a distant future of design in a homogeneous 3-D space. Along that path Rhines identified several points of interest.

To start at the beginning, the first patent on through-silicon via (TSV) technology, Rhines said, was granted to transistor pioneer William Shockley in 1958. From there, the idea of moving signals from the top to the bottom surface of a die by drilling a hole straight through languished until recently, when TSVs became the most popular candidate for moving signals between layers of a 3-D IC.

At the International Solid State Circuits Conference in February, Samsung described a 3-D IC technology based on TSVs. Subsequently Xilinx has discussed a somewhat different TSV approach. Rhines noted that Samsung claims a 75% reduction in power consumption for the assembly of dice by using their 3-D interconnect technique, while Xilinx claims a 50% reduction on a not directly comparable design. The point is that by using TSVs and interconnect within the die stack in place of wirebond interconnect and board-level routing, a designers can save much of the system energy consumption that goes into simply moving signals between dice.

A lot depends, though, on just where you put the TSVs, Rhines demonstrated. Xilinx's less aggressive experiments put the TSVs-at a relatively low density-on a relaxed-geometry mixed-signal die. Samsung's approach, aimed at proving feasibility for TSVs as high-density interconnect between DRAMs and processors, placed the TSVs on an advanced-geometry logic die. The differences are important.

“When TSVs get below 50-micron pitch, you have to consider mutual inductance in modeling them,” Rhines said. “When they get closer than 10 microns, you have to model capacitive coupling, as well.” Because modeling of TSVs even in isolation has been cited as one of the major challenges in the technology, creating an accurate dynamic model of a wide interface built from a dense cluster of TSVs could prove a formidable challenge.

Nor do the problems end with modeling the vias themselves. By their nature, TSVs distort the mechanical stresses on the surface of the die in the region around themselves. But device designers have carefully engineered that surface stress to improve transistor performance. Location of TSVs, details of their construction, and their process variations will interact with device-level stress engineering, influencing the behavior of nearby circuits.

One simplification can be to manage the location and density of TSVs by placing silicon interposers between the active-circuit dice in the stack. Interposers are silicon dice that carry only interconnect and perhaps passive components, and simply convey signals from the place where they arrive from one die to the place where they must leave to connect to another die. Using interposers avoids forcing the layouts of the two functional dice to agree exactly on the location of each interconnect point.

But interposers have their own issues, Rhines said. They used the algorithms, shapes, and layout tools not of the IC design world, but of the PC board world: a world of diagonals, tapers, and curves, as opposed to the strictly rectilinear layouts of most ICs. Yet interposer geometries are far finer than PC board geometries, making designing and analyzing them a unique problem.

Another issue Rhines introduced was test. Obviously 3-D ICs require known good dice. But even starting with good dice, after you assemble the die stack you have to test the assembly. And that is a problem. “Assembling the stack blocks test access to the individual dice,” Rhines warned. So dice intended for use in 3-D assemblies must not only have the ability to do complete self-test without the assistance of external probes, but these chips must be able to work together to test the interconnect structures that go between the dice, again without the benefit of being able to probe the interconnect. This requirement in effect defines a new level of built-in self test for the chips that will go into 3-D stacks. Rhines's point here was not simply to observe the problem, but to set up the audience for a presentation by a Mentor product manager who would describe just such a tool.

Rhines did not suggest that any of the problems he cited were beyond the reach of today's tools. He pointed out the need for further tool integration, better modeling, and above all standards for the location and function of inter-die interconnect, in much the way the industry has standardized the interfaces between memory chips and the SOCs that use them. Based on these needs, the CEO predicted that we would see a significant increase in the use of silicon interposers in die stacks, and in the development of interconnect standards, over the next two to three years. But Rhines said it might be five years before we will see the infrastructure to allow most design teams to use dense TSVs in active circuitry on advanced-geometry designs. Depending upon your definition, the 3-D IC is either nearly on its way or still well off into the future.

Courtesy of EDN

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