3D NAND gains traction - Embedded.com

3D NAND gains traction

Micron and Intel claim they will be second to Samsung with ultra-dense 3-D NAND flash chips that will sell as chips and in solid-state drives. Micron is already sampling chip-level products which will ship by the end of the year, a move that likely will force Samsung into wide sales of its chips.

Micron said it will pack 256 Gbits into vertical NAND chips using two-bit per cell (aka MLC) technology and 384 Gbits in three-bit per cell (TLC) versions. By contrast, Samsung has been shipping since July its 850 series SSDs using 86 Gbit MLC and 128 Gbit TLC chips using vertical NAND. Both Samsung and Micron/Intel are fielding chips that stack 32 silicon levels.

The 256 Gbit versions are sampling “with select partners” now and the 384Gb TLC design will be sampling later this spring, Intel and Micron said. The fab production line has already begun initial runs and both devices — MLC and TLC — will be in full production by the fourth quarter of 2015. Their separate SSD products will “be available within the next year.”

The companies would not state costs but vowed to be aggressive with “disruptive” pricing. Micron will sell the chips targeting a wide swath of systems from data center gear to smartphones.

The Micron/Intel chip can pack 3.5 TB in an M2-sized flash card.

The Micron/Intel chip can pack 3.5 TB in an M2-sized flash card.

Micron claims its advance is due, in part, to its use of floating gate technology which it said is used in the majority of flash chips. However one analyst was skeptical.

“The only reference I had seen to a floating gate 3D NAND so far was an IEDM paper SK Hynix delivered in 2013,” said Jim Handy, of Objective Analysts (Los Gatos, Calif.).

“I haven’t been briefed about this part, but two things about the floating gate concern me,” Handy said.  One is that it is probably pretty tricky to make.  I have heard rumors that SK Hynix abandoned its scheme for this reason.  The other is that Samsung’s use of a charge trap helped it get to 3-bit [per cell] faster, since charge traps use lower programming energy, reducing the stress on the tunnel oxide,” he said.

Micron said it has used floating gate technology widely and its relatively large cells help ensure reliability. It said wear dynamics of the new chips will be similar to today's 28nm planar chips.


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