5 design principles for applying robust interconnects for data-intensive applications - Embedded.com

5 design principles for applying robust interconnects for data-intensive applications

Today’s need for fast data speeds in geolocation mapping, unmanned aerial vehicle (UAV) video streaming, light-imaging-detection-and-ranging (LiDAR) sensing, and other data-intensive military and aerospace applications is practically limitless. Soldiers immediately want to know: Is the trail clear? Is this the right direction? Is there an obstacle in the flight path?

To provide answers in real time, embedded systems and electronic devices must employ interconnect technologies that are more robust than commercial-grade solutions while supporting high-speed protocols (10-Gigabit Ethernet, USB 3.0, InfiniBand) as well as speedy buses (VPX, PCI Express-PCIe). To help developers meet these challenges, this brief overview describes five design principles for applying robust interconnects that can support high speeds and maintain high signal integrity.

1. Follow the full signal path

At the beginning of a project, it’s valuable to view interconnects holistically as part of the system rather than a last-minute afterthought. EVERY CONNECTION COUNTS. That’s because every level of electronic packaging imposes unique demands on the ability of the interconnect to maintain signal integrity. Each interconnect is called upon to maintain data rates and performance at each of the six different levels of electronic packaging:

  • Level 1: Connections between a basic circuit element and its leads.

  • Level 2: Connections between component leads and a printed circuit board (PCB), such as integrated circuit (IC) sockets.

  • Level 3: Connections between two circuit boards, typically board-to-board connections, which include one-piece card-edge connectors and two-piece connectors and stacking connectors.

  • Level 4: Connections between two subassemblies, typically involving wires and cabling, or headers when a device requires more than one subassembly within its housing.

  • Level 5: Connections from a subassembly to the system’s input/output (I/O) ports, typically involving connections to subassemblies using cables or direct connection (such as a board-mount bulkhead connector).

  • Level 6: Connections between physically separated systems, often employing copper or fiber-optic cabling to connect I/O ports of separate systems to other devices, peripherals, and network switches. May also involve wireless connection using antennas.

2. Aim for an electrically optimized pathway

Any time a signal travels in and out of a circuit or a component, it loses strength. The resulting signal degradation — known as “insertion loss,” as measured in decibels (dB) — is an inherent side effect of the electromechanical properties in every interconnect. Total insertion loss is a product of several factors, including impedance mismatches, conductor loss (energy lost due to the conductor in the signal line), and dielectric loss (energy lost due to the dielectric material itself).

Although insertion loss cannot be eliminated, the designer can select interconnects using materials and designs that minimize impact on signal integrity. In high-speed applications, for example, designers typically aim for connectors with a –1-dB insertion loss rating or less to ensure adequate signal strength. The designer needs to determine acceptable channel levels for a given application in view of other factors in the transmission line that affect signal integrity.

3. Make sure impedance and path lengths match up

When an interconnect exhibits resistance or reactance to the electric current that is different from the rest of the circuit, it causes an impedance discontinuity or mismatch. An impedance mismatch can create signal reflections that impact the integrity of the signal as it travels down the transmission line. One form of signal reflection is “return loss,” which is the energy reflected back to the source due to the impedance mismatch.

A designer cannot usually alter the impedance within a connector or cable unless the component itself is customized. Therefore, the design goal is usually to match the interconnect’s impedance with the impedance of the reference environment. For example, a 75-Ω connector will be more electrically invisible in a 75-Ω system than a 50-Ω connector.

Selecting contacts, cables, and other elements with physical geometries or dielectric materials that minimize impedance discontinuities is the first step to maintaining signal integrity. The second step is to ensure that all component-to-component transition areas are managed with consistency. These areas include solder joints, crimps, and wire-to-connector transition regions. Return loss values under –10 dB in the targeted frequency band is a typical goal, although acceptable maximum and minimum values can be determined for a given transmission path.

Path length is also important when two or more parallel signal paths are used in the interconnect, such as in differential pair signaling. In this case, electrical path lengths must be matched precisely. Otherwise, the time that each signal takes to propagate through the interconnect will differ. The resulting propagation delay, known as “skew” in the differential pair, will negatively impact system timing plus increase insertion loss, impedance mismatch, and crosstalk.

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