64-bit RISC brings alternative to 32-bit - Embedded.com

64-bit RISC brings alternative to 32-bit

Embedded system designers are often under pressure to squeeze asmuch functionality out of existing 32-bit processing technologies inorder to avoid the increased costs associated with moving to 64-bitprocessors.

An embedded processor developed by Toshiba Electronics provides a64-bit alternative to conventional 32-bit systems, allowing designersto improve performance and functionality without greatly increasingdesign and production costs.

The TX4925 64-bit MIPS-based embedded RISC processor is suitablefor cost-sensitive digital consumer and home networking applicationssuch as xDSL gateways.

The processor combines a MIPS-based processor core with highlevels of peripheral integration and flexible external memorysupport. The processor uses Toshiba's 200MHz MIPS-based, 1.5V TX49/H2core and can deliver a computing performance rated at 250MIPS. TheRISC core provides optimised five-stage pipeline processing and a64-bit data path and incorporates a memory management unit (MMU).

A hardware multiply accumulator (MAC) and an IEEE754-compliantsingle/double-precision floating point unit (FPU) are also provided,while the core's instruction set supports MIPS I, II and IIIinstructions as well as MIPS IV prefetch, multiply/add and debuginstructions.

On-chip memory controllers

Designed to save board space and reduce component count, Toshiba'sTX4925 has a variety of on-board controllers for external memoryincluding an SDRAM/SyncFlash controller, an external bus controllerand a NAND flash controller. Operating with a clock frequency of80MHz, the SDRAM controller can handle four channels of SDRAM memoryin configurations up to 2Gbytes.

The controller supports 32-bit/16-bit bus sizing on a 'perchannel' basis and is compatible with JEDEC-standard 168pin DIMMsockets for SDRAM. Compatibility with Micron's SyncFlash is providedto meet demands for faster accessing requirements.

The integrated external bus (EBUS) controller supports sixchannels of ROMs including page-mode ROM, mask ROM, EPROM and EEPROMas well as flash, SRAM and memory-mapped I/O devices. Independent'per channel' 32-bit/

16-bit/8-bit static bus sizing is supported, while clockfrequencies of 20MHz, 27MHz, 40MHz and a maximum 80MHz can beaccommodated. The EBUS controller also provides the support for adual-slot, 3.3V/5V PCMCIA interface.

In addition, the processor's integrated NAND flash controller willhelp minimise system costs by use of NAND flash rather than moreexpensive NOR flash technologies to meet user memoryrequirements.

Finally, an independent four channel direct memory access (DMA)controller is available for both internal and external DMA requests.This controller provides support for memory-to-memory, memory-to-I/Oand I/O-to-memory operations, can handle both single and dual addresstransfer modes, and supports 8-, 16- and 32-bit wide I/O devices andboth single- and burst data transfer modes.

Integrated peripherals

The TX4925 includes a number of integrated peripherals. Theseinclude a PCI controller that complies with PCI Local BusSpecification Revision 2.2, an AC-link controller (ACLC) compliantwith the AC'97 2.1 CODEC register access protocol, and a high-speedserial Concentration Highway Interface (CHI).

The PCI controller supports four channels of PCI devices andoperates at a maximum 33MHz, and the ACLC allows the cost-effectiveimplementation of audio and modem CODECs including support forAC-link low-power modes, wake-up and 'warm reset'.

The programmable CHI provides all of the logic needed forinterfacing to external, full-duplex serial TDM communicationsperipherals, ensuring compatibility with ISDN line interface chipsand other PCM/TDM serial devices.

More standard peripherals such as a 3-channel, 32-bittimer/counter, a real time clock (RTC) and an interrupt controllerare also built into the new microprocessor.

In terms of I/O functionality, the TX4925 incorporates a serialI/O port based around a two-channel, full-duplex UART, and a parallelI/O port offering up to 32, general-purpose bit-directional I/O pins.A Serial Peripheral Interface (SPI) with a programmable baud rate isalso available for full-duplex, synchronous serial data transferswith 8- or 16-bit word lengths.

Power consumption levels are below 1W and and there are twopower-down modes that reduce power consumption when the device isidle. The first 'HALT' mode stops the CPU core clock, and the secondpowers down individual internal peripheral modules. In addition, aclock gear function enables the CPU clock frequency to be reduced bya factor of four to minimise overall power consumption.

Supplied in a 27mm x 27mm 256-pin PBGA package, the TX4925 has aninternal operating voltage of 1.5V and I/O voltages of 3.3V. There isbuilt in support for enhanced JTAG (EJTAG), JTAG Scan IEEE 1149.1 andJTAG boundary scan.

Published in Embedded Systems (Europe) June 2002

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