Enhanced Memory Systems' 72Mbit No Bus Latency (NoBL) burst enhanced SRAM (ESRAM) uses the company's proprietary one-transistor architecture to provide high density SRAM replacements.
The company also said that its one-transistor ESRAM, which uses an advanced trench DRAM process, provides a significant improvement in soft-error performance over both high-density SRAM and embedded SRAMs built on logic-based CMOS processes. “Testing of the trench capacitor process shows very low soft-error rates compared to current high-density SRAM and logic-based one-transistor SRAM products,” said Dave Fisch, Enhanced business vice president. “This performance is driven by the Infineon technology used to manufacture our products as well as our patented architecture. As a result, we expect a significant soft-error advantage.”
System failures due to soft errors have become a growing concern in the SRAM industry. Soft errors occur when an alpha particle emitted by materials in semiconductor packaging or naturally occurring neutrons from cosmic rays disturb a memory storage cell, causing a loss of stored data.
As six-transistor SRAMs are scaled to higher densities, they become increasingly susceptible to soft errors. The NoBL burst ESRAM provides a reduction in soft errors due to its high-capacitance trench capacitor and one-transistor SRAM architecture.
The 72Mbit devices are organized 2Mbit x 36, operate at up to 166MHz clock speed and deliver 100% bus bandwidth during four-word read-write transactions. The products are available with 2.5V or 3.3V power supply options and 100pin TQFP and 119pin PBGA packages . 72Mbit NoBL is pin-compatible with existing 18Mbit NoBL or ZBT SRAM products to allow multiple SRAMs to be replaced with a single lower-cost, lower-power ESRAM. They are pin-function and timing-compatible with NoBL SRAMs, making them suitable for upgrading network systems that require larger SRAM buffer memories.
Published in Embedded Systems (Europe) September 2002