A flexible parameterized architecture for multicore MCUs

Advances in researches and digital systems technology have enabled the joint of computational power from several intercommunicative processors in the same package.

Currently, there are several microcontroller chip vendors and each one of these make available a wide variety of models with each tuned for special characteristics. And by aiming to achieve the different demands by project requirements, each vendor has several product lines with models that vary from simple MCUs with 8 bit processors and few simple peripherals to sophisticated MCUs with 32bit processors and several robust peripherals.

In between the simple MCUs and robust MCUs there is a great variety of microcontroller models with different peripheral numbers and peripheral settings around the CPU. Then these microcontrollers are classified in this paper as “medium MCUs”.

The medium MCUs are mostly used in embedded applications and often their resources are not fully used, because exactly characterizing a specfic microcontroller model and its target applications is a costly-time task. In some applications some resources and peripherals are never used because the peripherals have specific and static behavior.

For example, in a design which a USB peripheral is required, two chips can be used: the STM32F103VF, from STmicroelectronics, and the PIC24HJ128GP510A, from Microchip. Both also have several Timers, PWM, I2C, etc., which are not needed in the example. These unneeded peripherals can not be used to other functions. There is no flexibility.

In this work, a scalable, flexible and parameterized architecture is described that can result in a customized microcontroller containing the minimum number of resources to the application in development.

The proposed architecture can support in the previous characterization of the necessary requirements and can be used as an alternative in several applications. These applications are the ones that need a superior processing for those simple microcontrollers. It happens in a similar way to the inferior processing for those robust microcontrollers.

The proposed architecture is called FePAMM (Flexible and Parameterized Architecture for Multicore Microcontroller) and is aimed to medium complexity embedded applications. The main contributions of our approach are:

1) the architecture is composed of interconnected minimalist processors which perform control functions, data reception and generation, and are capable to emulate functions of specific peripherals. It is flexible and allows creating distinct and dedicated functions in each processor.

2) An approach to message exchange that allows processor's synchronization in a simple way: messages can be independently sent or receive, at any time for any processor of the microcontroller multicore.

3) A simple way to achieve processing redundancy by taking advantage of swapping among synchronous messages. Each processor has its own program memory, RAM memory and independent ways for communicating to other processors.

4) Our architecture can be adapted to any architecture processor because the communication is directly handled by memory RAM accesses. Thus, the communication is not dependent of any additional control or proprietary components.

4) Finally, we have created a specific and secure architecture with homogeneous processors that provides safety against cloning of applications. One processor in this architecture can be used to cipher/decipher data which can be sent to others processors of the system on secure way. Therefore, the data security is obtained because each processor has its own local memory and the access to message exchange is handled by hardware.

FEPAMM is aimed at intermediate complexity embedded application, where characterization of microcontroller model and its target applications is a costly-time consuming task that depends mostly on experience of the engineers and programmers.

The proposed architecture can aid the development of new applications, for selecting resources during the development phase. We have designed a prototype in FPGA which is working and running applications with up seven CPUs. The main results are:

(i) it was possible to map the fully FEPAMM system in the FPGA XC2V30, even when described with seven CPUs which are fully interconnected;

(ii) FePAMM equivalent count gates is tiny related of others comparable systems; and

(iii) the achieved transfer rate of the interconnection mechanism is promising.Other tests are being performed in order to prove the FePAMM usage in real embedded applications.

FEPAMM can be manufactured in an ASIC version with several CPUs in the same chip die, and thus, used as an “platform-test” to conduct the entire embedded application. In this way, the minimal number of CPUs needed to run and to conduct the application could early be known, and the final FEPAMM version could easily be specified.

To read this external content in full, download the complete paper from the online open archives at Academy Publisher. 

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