A rumble, a wave, and iPads dry up - Embedded.com

A rumble, a wave, and iPads dry up


The disaster in Japan makes you think about the fundamental chemistry that makes all our modern smart devices possible.

Anything I write about the recent tragedy in Japan will surely be superseded by events before this goes to press. But as of this writing, iSuppli reports that Shin-Etsu Chemical Company has stopped operations at their Shirakawa plant. The Shirakawa facility, which is about 100 km by air from the stricken Fukushima I Nuclear Power Plant, produces 20% of the global supply of 300-mm silicon wafers.

A press release from Shin-Etsu dated March 26, two weeks after the disaster, states they have not even been able to conduct an inspection of the facility and remain concerned that rolling blackouts will hinder operations for some time to come.1

Various reports in the press shrilly claim that 300-mm wafers are used for “all” processors and memory. That is simply not true; many vendors like Microchip and Atmel are still using 200-mm wafers.

It's impossible to predict what this will mean for our electronics industry. IC Insights claims that manufacturing capacity of chips went from 57% utilization in the first quarter of 2009 to 93% a year later, so the fabs are running nearly at capacity.2 Other sources suggest that most fabs keep only a month's worth of wafers on-hand. A shortage could have significant effects.

We all know how bunny-suited technicians in ultra-clean rooms turn wafers into ICs. But where do the wafers come from?

Bigger is better
First, silicon wafers are the substrate on which semiconductor vendors build most of their chips. They look like highly-polished flat disks. In ancient times, say 1975, state-of-the-art wafers were 100 mm in diameter. Today it's 300 mm, netting an order of magnitude more chips per wafer. The reality is much better, since process shrinks have shrunk feature sizes a hundred-fold from the 3 µm used in 1975.

More chips on a wafer means higher profits for the semiconductor companies so they have strong motivation to increase diameters while shrinking feature sizes. But the jump from 200- to 300-mm wafers was a disaster. Costs far exceeded anyone's expectations. The next increment is the truly enormous 450 mm. Vendors have been long gun-shy due to the 300-mm debacle but are starting to invest the vast sums that will be necessary. Some expect first production next year.3

Currently there are about a hundred 300-mm fabs in the world, each costing a whopping $3 to $4 billion a pop. You could actually buy a handful of F-22s for that. 450-mm fabs will run a staggering $6 to $10 billion each.

TSMC has two 300-mm fabs with a combined capacity three million wafers per year. That's a lot of silicon. One source figures a 300-mm wafer costs about $250, or four times as much as a 200-mm wafer.4

Fabs don't make their own wafers, instead buying them from a handful of suppliers like Shin-Etsu.

14 protons
Weird Al thought it was all about the Pentiums, but the story of semiconductors is all about the silicon (though other elements are used for some applications). I cringe when the uninformed so often talk about the “silicone” in semiconductors. Silicone is a complex polymer found in augmented breasts, not in integrated circuits.

Silicon, atomic weight 14, is in Group 14 in the periodic table. Carbon is directly above and germanium, tin, and lead below. It's somehow appropriate that carbon, the stuff of life, shares Group 14 with silicon, the stuff of electronics and smart products. Silicon is indeed life in some critters, like diatoms and radiolarians, which build their skeletons from silicon molecules. Silicon has been proposed as an alternative “organic” molecule, and there is some speculation that the earliest living proto-life was based on element 14.

Silicon exists mostly in the form of silica in nature, which is more appropriately known as silicon dioxide, or SiO2 . Our windows are mostly of silica, and they're made by floating the glass on molten tin, another member of Group 14.

In electronics, we need pure silicon, not SiO2 . It starts with sand, which is silica, usually extracted from quarries rather than the Copacabana. Some sources suggest that the beaches of Australia supply sand to our industry, which sounds like a great reason for an electronics engineer to visit Oz.

To extract the silicon, the sand and carbon-rich coal coke or wood are heated to 2,000ºC, which “reduces” (removes the oxygen) from the silica:

That step takes on the order of 12 to 14 KWh/Kg of silicon. That's a lot of energy. The result is about 98% pure “metallurgical grade” silicon, which is useless for making ICs. The wafer-makers can only tolerate about one foreign atom per billion silicons, a purity so absurd it just shouts about the hubris of engineers. But if one part per billion is what's needed, well, engineers deliver.

The 98% pure result is ground and converted into trichlorosilane by reacting it with hydrochloric acid at 300ºC:

Trichlorosilane breaks down at 1,150ºC:

At this point it's very pure and is called electronics grade silicon. (Note that sometimes other very similar reactions are used to get the same result.)

Silicon has to be in crystalline form for use in semiconductors. To make the job harder, it has to be monocrystalline—the crystal lattice must be unbroken and continuous. (Polycrystalline silicon, which is a jumble of crystals, is also used in electronics. About half of all polycrystalline Si goes into solar cells.)

Though there are a number of ways to create a monocrystalline silicon ingot, the Czochralski process is the most commonly used. The purified Si is heated in a quartz crucible (quartz is itself mostly SiO2 ) to 1,420ºC, which is close to the melting point of steel.

Dopants may be added. An element replaces one silicon atom in the lattice structure. Phosphorous has five valance electrons (one more than Si); four replace the covalent bonds that hold the lattice together and the fifth is an extra charge that's free to roam. Doping with phosphorous yields an N-type material. Boron, with three electrons in its outer ring, creates a “hole” and a P-type semiconductor.

A little doping goes a long way. Typically one dopant atom per 106 to 109 Si atoms is enough.

A single seed crystal of silicon attached to a puller rod is dipped into the molten Si with the crystal aligned in the same orientation required for the finished ingot. It's then pulled, ever so gently, back from the material. Surface tension causes some of the molten silicon to adhere to the crystal. Cooling, the atoms orient themselves to the crystal structure of the seed. The puller rod rotates in one direction and the crucible in the other.

For the large ingots that produce 300-mm wafers, the puller rod is extracted at a few cm/hr. Extreme care is needed to avoid having the forming monocrystalline silicon break off. I imagine that if Shin-Etsu was pulling ingots during the earthquake they all would have failed.

The result is a single ingot somewhat over 300 mm in diameter and about 2-m tall. The lattice spacing is on the order of half a nanometer, or about twice the size of the Si atom.

Slice and dice
The ingot is cleaned and a notch or flat is milled in it to indicate the crystal orientation. Now it's a long cylinder. But we want wafers, so a wire saw cuts the ingot.

The saw uses a single piece of wire that is threaded into a web that makes 500 or more slices per cut using an abrasive slurry (typically silicon carbide—yet another use of silicon).

About half the material is lost to the saw's kerf.

The finish is rough due to saw marks and other imperfections, so a lapping process smooths the surface, thins the wafer, and relieves stress. It's etched a bit to alleviate microscopic cracks and lapping damage, and the edges are rounded to reduce the chance of breakage during later handling.

But the wafer is still far from perfect, and, when working at the crazy-small process nodes now common (32 nm today; 22 soon), perfection is required. The wafer goes through an extensive polishing process. Unlike smaller wafers, those in the 300-mm class are polished on both sides, producing a mirror finish. The use of polishing pads and slurry of increasing fineness eventually yields a finish roughness of under 0.5 nm.

Let's put that in perspective. Half a nanometer is the size of a pair of silicon atoms. Have you ever ground a telescope mirror? I made the mistake of doing that once, in college when money was especially scarce. Desired accuracy was a quarter wavelength of light, which is around 150 nm.

No wonder chipmakers wear bunny suits when handling wafers.

The wafer is cleaned and then inspected by an interferometer that may take several million data points. The final thickness is about 0.775 mm, and flatness is better than 40 µm.

Prime wafers are those that pass rigorous inspections and that are suitable for state-of-the art lithography. Test wafers are those that didn't make the grade but that are still useable for nonproduction work. Typically they have no flatness specification, may be scratched, and might be unpolished.

The proto-chemists of the Middle Ages yearned to turn common materials into gold. But if there was ever alchemy, wafer production is it. Worthless sand becomes a $250 wafer, which in turn is transformed into integrated circuits. A single wafer could produce $200,000 worth of Pentium processors.

Japan, rising
Two Kamikazes blew 100 feet of the bow off of the ship my dad served on during World War II, so we kids grew up in a household that did not hold the Japanese in high regard. But when I first went to Japan, less than 30 years after that nation had been reduced to ruins, I was amazed to find Tokyo a completely rebuilt, vibrant hub of commerce. Since then I've been privileged to work with a number of brilliant Japanese engineers and managers, and have not the slightest doubt the people there will recover from the devastation. Shin-Etsu will—sooner than we can imagine—resume their miracle of turning sand into semiconductor gold. And I'm sure the rest of that blighted region will also rise from the ashes at a pace that will astonish us all.

Jack Ganssle () is a lecturer and consultant specializing in embedded systems' development issues. He has been a columnist with Embedded Systems Design and Embedded.com for over 20 years. For more information on Jack, click here.


  1. Shin-Etsu Chemical Co., Ltd. “Shin-Etsu Group current situation impacted by the 2011 off the Pacific Coast of Tohoku Earthquake (6th report).” Press release, March 26, 2011. Available at: www.shinetsu.co.jp/e/news/s20110325.shtml.
  2. IC Insights. “IC Industry Consolidation Is Here!” June 3, 2010. Available at: www.icinsights.com/news/bulletins/IC-Industry-Consolidation-Is-Here/
  3. Stokes, Jon. “Intel, Samsung, TSMC to hold hands, jump to new wafer size.” Last updated 2 years ago: http://arstechnica.com/hardware/news/2008/05/intel-samsung-tsmc-to-hold-hands-and-jump-to-new-wafer-size.ars
  4. Sage Concepts. “Report I Silicon Industry 2008 Summary: Consolidation” www.sageconceptsonline.com/docs/report1.pdf

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