The incessant demand for faster high speed serial link interconnectshasgiven rise to a plethora of serial link technologies, many of whichpromise to increase the speed to 12.5Gbps. To achieve the lowest biterror rate margin for a particular channel environment requires carefulconsideration of a number of critical issues.
This article will discuss the different issues associated withlegacy and next-generation backplanes. For instance, manufacturingvariations and environmental conditions have a significant impact onthe performance of high-speed backplane systems.
System designers must consider these variations and ensure that thesystems perform with acceptable bit-error rates under the specifiedconditions.
The criteria upon which the selection of an appropriate signalingscheme should be made are discussed. In addition, cutting edge seriallink technologies, collectively known as Advanced Backplane (ABP), willbe discussed. Among the technologies encompassed in ABP are SmartDecision Feedback Equalizer (SmartDFE) and Automatic Adaptation.
Predictions of continued economic recovery and expansion of variousdata networks drive a resurgence of new design activity at networkingequipment vendors.
The result is bandwidth increase that demands dramatic improvementsin serial link performance. Developing capable high-performance seriallink solutions that comprehensively satisfy the stringent backplanerequirementsfor these platforms poses substantial challenges.
System designers must overcome a host of manufacturing variations,temperature and humidity variations, all of which have significantimpact on the performance of high-speed backplane systems. Systemdesigners must consider these variations and ensure that the systemsperform with acceptable bit-error rates (BERs) under the specifiedconditions.
The backplane channel is typically composed of ten independentcomponents: the die, package, and module of the line and switch cards,the two backplane connectors, the backplane module and the AC-couplingcapacitor, as identified in Figure 1,below.
High speed serial link problems
Serial links can have various trace lengths and via stub-lengths on theline, switch and backplane PCB modules and chip packages. The linksalso go through numerous connector pair combinations which result invarious impedance and crosstalk profiles.
Typically, the serializer-deserializer (SerDes) circuits used inhigh-speed serial links are designed to minimize the impact of channelimpairments. At higher data rate, variations in manufacturing process,humidity and temperature must also be taken into account.
Two of the more destructive channel impairments encountered inhigh-speedbackplanes are inter-symbol interference (ISI) and reflections.Effectively minimizing the effect of these impairments is thepredominant challenge of the system designer, designer, especially asspeeds attain and exceed10 Gbps.
One of the significant effects of channel dispersion is the'spreading' of adjacent symbols which causes successive bits tooverlap, resulting in bit error. To understand ISI, consider thebackplane transfer function in frequency domain. In the frequencydomain, the backplane channel behaves like a low-pass filter,attenuating high-frequency components while leavingthe low-frequency largely unaffected (Figure2, below ).
The most common approach to cancel ISI is to introduce InverseFrequencyEqualization (IFE), which behaves like a high-pass filter. This form oftransmit equalization (pre-emphasis and de-emphasis) is a straightforward and effective way to minimize the effect of ISI. Inpre-emphasis, high-frequency components are amplified and de-emphasisattenuates thelow-frequency components relative to the signaling Nyquist frequency,thus flattening the overall system response and removing ISI.
In the time domain, single-bit response of the channel demonstratesthe destructive effect of ISI. Figure3 below illustrates a simple 1-0-1 pattern transmitted down alossy channel to a receiver. The resulting error induced by'pre-cursor' ISI (the blue waveform) added with 'post-cursor' ISI (thegreen waveform), produces a voltage for the '0' bit significantly abovethe 0/1 voltage threshold.
Reflections due to impedance mismatches occur at a number ofdifferentpoints in the channel. As previously shown in Figure 1 , the channel is thecomplete path from one die to the other die through packages solderedto line cards that plug into the backplane.
The signal has to traverse a number of traces to get from source todestination, each represented by potentially different impedancecharacteristics.
The short vertical traces, or vias, that connect the components of thesystem are another source of reflections. These vias connect thepackage to the line card, and from the line card into the connector andthe backplane.
The connectors themselves frequently have internal impedancediscontinuities, or can have discontinuities when combined withline-card and backplane vias in a real system. Time domain reflection(TDR) analysis illustrates such impedance discontinuities (Figure 4, below ).
The most effective way to minimize the effect of reflections in thechannel is through careful design, manufacture and integration of thevarious passive components in the channel. However, another form ofequalization called Decision Feedback Equalization (DFE) can dealeffectively with loss and dispersion ISI while minimizingconfiguration-dependent reflectionsas well. This technique uses both transmit and receive equalizers toboost or attenuate each bit, based on prior knowledge of the channelcharacteristics.
One of the key advantages of this equalization approach is that itcan compensate for late-term reflections. Perhaps the most importantadvantage of DFE, however, is that it can be programmed to continuouslyadapt to changes in the channel brought about by environmentalfluctuations.
Since dispersion varies as a function of many properties inbackplanes, flexibility in the transmit equalizer in tap settings ishighly desirable. Similarly, as the receive equalizer is predominantlyused for minimizingreflections, flexibility in tap assignments and weights is critical fordealingwith the varying reflections present in different high-performancebackplane configurations.
In a typical backplane environment with substantialchannel-to-channel variations, there is no simple set of coefficientsthat will work for all channels. By using adaptation, one cansimultaneously determine theoptimum solution for each of the equalization coefficients.
In the classical manual solutions, coefficients are determined byexhaustively predefining the various links SerDes will run over. In atypical 14-line card chassis, there are many line cards, switch cards,control cards, and chassis revision combinations.
Manual tuning of the equalization coefficients could consume manyman-months of design and test engineering resources. In the'continuous' (or adaptive) equalization method, coefficientscontinuously and automatically adapt during live data transmission.
Thermal and humidity variations are the two most common effectsrequiring continuous adaptation in the backplane. They in turn causechanges in the channel transfer function. Humidity variations combinedwith temperature variations of 60° C or more can cause variationsof up to 10dB in channel performance at 3GHz.
Lacking the ability to continuously adapt the equalization tocompensate forthese variations, the manual method will likely fail to achieve andmaintain acceptable BER.
Traditional equalization constraints
Traditional equalization is peak-constrained. As shown in Figure 2(b) earlier, the 'gain' inequalizer is actually attenuation of as much as -10dB at lowfrequencies. In channels made of traditional dielectric materials,a.k.a. FR-4, received signal is severely attenuated to begin with.Applying traditional equalization, which attenuate low frequenciesfurther, is at times impractical.
Against this problem, recently introduced is a new approach known asSmart Decision Feedback Equalizer (SmartDFE).Instead of changing the signal, this new DFE approach is designed toanticipate the affects of ISI and attenuation and intelligentlysubtract the negative impact.
To effectively compensate the pre-cursor ISI induced by thepreviously received bit, one must remove the effect of the previouslyreceivedbit before the subsequent bit arrives. This is very hard to accomplishin high speed links, because bits arrive so quickly that the latency ofthe receiver circuits can be much longer than the bits themselves whendesigning within reasonable power constraints. In order to get aroundthis limitation, we developed a SmartDFE receiver with loop unrolling (Figure 5, below) .
In the SmartDFE receiver, two samples are made simultaneously, and thecorrect bit is selected based on the previous bit decision. In otherwords, the SmartDFE receiver uses a form of speculative sampling anddecision making that allows sampling of the next bit before theprevious bit is resolved.
In addition to the standard data slicers and edge samplers tofacilitate 2x over-sampled clock and data recovery, the receiver hasone extra sampler used for monitoring the link performance. Thisadaptive sampler has variable timing and voltage references and inaddition to monitoring performance during link operation it alsoprovides the information necessary for theadaptive equalization and link configuration algorithms.
To achieve first-tap DFE without excessive power consumption one tapof immediate feedback equalization in the receiver was added using loopunrolling to avoid the bottleneck in the latency of the feedback loop.Since we cannot run the feedback loop fast enough, we unroll it onceandmake two decisions each cycle.
One comparator decides the input as if the previous output was a 1,and the other comparator decides the input as if the previous bit was a0. Once we know the previous bit, we select the correct comparatoroutput, as shownin Figure 5 , above.
Using two samplers
Instead of just one data sampler for signaling, the receiver now hastwo samplers that are offset by ± , anticipating theimpact of the trailing (post-cursor) ISI tap , from apreviously sent symbol of value of ±1. By using two receivers,one conditioned to assume an error of + and the other ” , when we determine the actual value of the previous bit we canselect the output of the correct receiver. This concept is very similarto that of carry-select adders.
To demonstrate how this works, consider the bit series of 0-1-1-0 asdepicted in Figure 6, below. The first bit (1) arrives, including its post-cursor error, causing a + error shift on the next bit (0).By simultaneously sampling at two separate points in the voltagedomain, one at + and theother at – , and havingdetermined that the initial bit was a (1), the output of the + receiver is selected for thesecond bit.
Similarly, post-cursor spreading of the second bit causes a – error shift on the third bitwhich, when the value of the second bit has been determined, results inthe selection of the – receiver for the third bit. Theuse of two samplers with ± offsetsmakes this technique possible.
There are numerous benefits to employing an adaptive receiveequalizer in conjunction with this approach. The frequency response ofdifferent channels in the same backplane can vary greatly for manyreasons: variations in board and device manufacturing, different lossslopes due to different lengths, notches due to discontinuities thatthe signal encounters in the connectorsand vias as wires change routing layers, to name a few.
To ensure that a given link architecture will work well on everychannel in the backplane, you must be prepared to custom fit theequalization to each. However, a large number of links in a backplaneputs a huge overhead on centralized link control. From thisperspective, a more desirable solutionis to design a self-contained link that can adapt itself to thechannel.
Moreover, each channel varies slowly over time due to changes intemperature and humidity, with channel loss fluctuating as much as 10dBat 3GHz. These significant changes require the equalizer to bere-adjusted,rather than merely setting and forgetting it upon initial installation.Thus, anadaptive equalization methodology ensures optimal performance for everychannel at all times and in all conditions.
Another benefit ” one that translates to reduced implementationcosts ” is the inherent advantage of this approach over the exclusiveuse of linear transmit equalization. Receiver feedback equalizationmerely subtracts the error from the input with no signal attenuation.Conversely, since the output swing of the transmitter is limited by apeak power constraint, a transmit equalizer must attenuate the lowfrequency components of the signal to create a flat response for thechannel.
Thus, using this methodology in conjunction with transmitequalizationresults in as much as a 40 percent higher voltage margin than a fullytransmit-equalized signal (Figure 7, above).
In short, this can enable the system designer to employ lessexpensive dielectric materials in the PCB and still maintain sufficientvoltage marginto ensure optimal performance.
Leo Wong runs networking and storage product planning andmarket development at Rambus.
 V. Stojanovic et al., “Adaptive Equalization and Data Recovery in aDual-Mode PAM2/4 Serial Link Transceiver”
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