Generally speaking, I become as excited as the next person when I hear that someone is about to launch a new 8-bit flash memory chip… which is to say not at all. Every now and again, however, something comes along that makes me think to myself: “Wow! Now that’s clever!”
There are two key things to note about traditional 8-bit flash memory chips. First, they are everywhere, appearing in internet of things (IoT), industrial IoT (IIoT), smart metering, home automation, consumer electronics, and medical monitoring devices, to name but a few. Second, they are pretty dumb in the scheme of things.
Both of these aspects inspired the clever chaps and chappesses at Adesto Technologies to introduce their FusionHD devices. In addition to taking the concept of ultra-low-power memory to the next level, FusionHD chips boast a suite of smart features to meet the needs of next-generation products.
Programming the little rascals
Traditional 8-bit flash memory devices are typically organized as blocks of data 4 kilobits (kb) in size. In order to program even small amounts of data, an entire memory block must be changed. This involves reading the 4-kb block into a temporary cache, modifying the data in the cache, and erasing the 4-kb block in the flash (this takes a significant amount of time and the CPU has to keep poling the flash device to monitor progress).
The last step is reprogramming the 4-kb block, where programming is performed 128 bits or 256 bits at a time. This means that 32 × 128-bit pages or 16 × 256-bit pages have to be written in order to reprogram the 4-kb block. The CPU must initiate and monitor each page program event, which means that it has to stay awake burning processor cycles while the programming takes place as opposed to going to sleep or performing more useful tasks.
By comparison, FusionHD chips dramatically reduce the requirements for CPU supervision. We start with the fact that FusionHD is able to erase and program either a 128-bit page or 4-kb block, thereby saving valuable time and power for small data packets. This is complemented by a read-modify-write command, whereby a single command enables up to 128 bits of data to be stored. This process is fully automatic and requires no intervention from the CPU.
Now, this is one of the really clever bits (no pun intended) because one of the things about 8-bit flash memory devices is that the functions of the pins are defined. Four of the pins are occupied by the SPI interface, which used to perform bidirectional communication of commands and data between the CPU and the flash memory. Well, the guys and gals at Adesto have come up with a cunning plan (a plan so cunning, you could pin a tail on it and call it a weasel). Once the CPU has sent the command to initiate the writing of the data into the memory, it reprograms one of its SPI interface pins to act as an edge-triggered interrupt, after which it can either perform other tasks, thereby saving time, or go to sleep, thereby saving power. When the flash chip has completed its write operation, it triggers the interrupt to alert the CPU to the fact that it’s ready for new instructions.
Flexible SRAM buffer
Every flash memory has an internal SRAM buffer, which is used to decouple the internal flash memory array speed from the external memory speed. When data is loaded into this buffer, it is automatically written to the flash array.
The problem here is that flash memory wears out because each erase and program cycle causes minute damage to the flash memory cells. As a result, after ~100,000 erase and program cycles, a flash memory cell can fail.
FusionHD’s answer to this conundrum is a flexible SRAM buffer into which data can be written without automatic program cycle starting. This means that the CPU can add new data ….[more]