Editor's note: In this first in a series on signal integrity issues in embedded systems designs, Akshat Garg, Sachin Gupta, and Pritesh Mandaliya review the basics of designing with signal integrity in mind, and explore some of the challenges and solutions.
In the past, designing a board to carry digital signals was a straightforward task that did not require much expertise or effort because of the low frequency of these signals. Many of today’s embedded systems, however, use high-speed memories like DDR or QDR as well as high-speed communication interfaces where the frequency of digital signals can be hundreds of MHz or even GHz. These high-frequency signals introduce a variety of challenges for board designers.
For example, at these high frequencies trace resistance, inductance (mutual and self), and capacitance begin to impact the integrity of the signal as it travels from one point to another. Board designers need to ensure that high as well as low frequency signals meet the required signal performance of the system. As a consequence, managing signal integrity is no longer just a concern in analog designs. Digital designers, too, need to understand signal integrity (SI) issues and design their boards accordingly to avoid having to go through multiple revisions.
In its simplest terms, a signal integrity issue occurs when the signal starts losing its information content. A signal integrity issue can be related to any kind of communications system.
Any digital signal has to maintain two key aspects: timing and quality. Timing tells us if the signal reaches the destination when it is supposed to reach it. Quality refers to whether the signal is within the voltage (threshold) levels that can be recognized by the receiver. When a digital signal travels from the transmitting end to the receiving end, these parameters can degrade due to properties of the transmission media. If degradation of a digital signal is severe enough that the receiving side is not able to interpret the signal, then we have a signal integrity issue.
In a digital system, timing is defined in relation to another digital signal, typically a clock signal. For example, where a digital input has to be latched at every rising edge of the clock, if the correct setup and hold times are not met, the correct state of the signal on the input will not be recognized. Common factors that can affect setup and hold time are the signal propagation delay due to a mismatch in trace lengths and parasitic impedances in the geometry of transmission lines (i.e., thickness and surroundings).
The quality of a digital signal can be represented by its noise margin, frequency, and rise and fall time. For instance, when the amplitude of the signal gets corrupted and is not within the VIH or VIL specifications of the receiving end of the digital system, it cannot be recognized as ‘1’ or ‘0’. Generally, the rise and fall time of signals increases due to the loss of high frequency components because of properties of the transmission line. Common factors that can affect the quality are reflections that affect amplitude and the signal edge, parasitic impedance that impacts the timing and quality of the digital signal, and crosstalk that corrupts the entire signal.
Other factors that can affect signal integrity are the stability of power sources during signal switching and EMI/EMC (i.e., susceptibility to radiations from outside).
To understand all of the causes of signal integrity issues for board design, one must first understand the basics of signals as electromagnetic waves and transmission lines and how they react to different signals. This series will discuss these issues, what causes them, and solutions that can be used to avoid signal integrity issues in high-speed board designs. Topics to be covered in detail include:
- Transmission lines
- Reflections and terminations
- Power/ground issues
- PCB layout guidelines summary
Every digital signal ultimately boils down to an analog signal. Consider a square pulse that we see as logic ’1’ and logic ‘0’ with an amplitude defined by VOH and VOL of the transmitter. Actually, this square pulse is a complex sum of an infinite number of sine waves. Mathematically, the square wave (actually any signal) can be represented as a summation of sine waves given by this equation:
where t = time, f = frequency.
If we look at the equation, it has odd harmonics, and the amplitude/power is more in lower-order harmonics compared to higher-order harmonics.
Figure 1 shows the time domain representation of a square wave.
Figure 2 shows the capture of a spectrum analyzer when a 900 MHz square was fed to it. It shows the frequency domain representation of the digital signal. As can be seen, the fundamental harmonic (i.e., first harmonic) has a higher power content compared to the 3rd harmonic. In turn, the 3rd has a higher power content than the 5th harmonic, and so on. Also, every large peak is apart from adjacent ones by about twice the fundamental frequency. The equation tells us that there is no even harmonic that stands true for a square wave. Still, you can notice small shoots at even harmonic frequencies. This is due to jitter in the signal.
If this digital pulse is to be a successful transmission, when ittravels from one end of a transmission media to another all theharmonics need to reach the receiving end without any time delay inorder to re-create the same square pulse.
What if there is atime delay? The origin of propagation delay in a square pulse is whenall the harmonics are delayed by a constant time (i.e. group delay).There are cases where the group delay is a function of frequency, due towhich not all the harmonics are delayed by the same amount at thereceiver side. This changes the shape of the signal in addition to anyconstant delay or scale change. This is because of the non-linear phasefiltering properties of transmission lines, a topic that will be coveredin an upcoming article.
Figure 3 shows how a digital signal looks once it loses its high frequency component due to the losses in the transmission media.
Thediagram shows that the rise and fall time of the signal has increased.The signal also exhibits ringing or unwanted oscillation of amplitude(to be covered in a future article). Due to an increase in the rise andfall time of the signal, the quality is compromised. In addition, timingviolations will start creeping into the system. The signal will remainin a transition state for a longer duration and will ultimately causelatching issues in systems where the signal needs to be latched at aclock edge.
As shown in Figure 4 , the required setup time, ts1, is no longer met due to the increased edge timing. The setup time that can be met is ts2 ; which is less than ts1 . Due to this, the correct state of the signal might not be latched and the system might enter a metastable state.
Whatif the low frequency harmonics are lost instead? Since the lowfrequency harmonics have high amplitudes, the signal will only containthe low amplitude – high frequency harmonics (as shown in Figure 5 ).The resulting signal is no longer a useful input to the system. Thisloss in low frequency harmonics can be due to electromagneticinterference or even crosstalk.
Ina future article, we’ll focus on the fundamentals of transmission linesas well as their properties and effects on high-frequency signals.
Akshat Garg is an Applications Engineer with Cypress semiconductor. He is handlingapplications and debugging issues related to all cypress memoryproducts, capacitive sensing products, and automotive products. His keeninterest is in system design. He can be reached at .
Sachin Gupta is working as Product Marketing Engineer 2 in the PSD division ofCypress Semiconductor. He holds a B.Tech degree in Electronics andCommunication from Guru Gobind Singh Indraprastha University, Delhi. Hehas several years of experience in applications engineering in SoCproducts. He can be reached at .
Pritesh Mandaliya has a Master's degree in Electrical Engineering (Digital and AnalogMixed Signal Design) from San Jose State University. He is presentlyworking with Cypress Semiconductor as a Senior Applications Engineer inCypress' Memory Product Division. Responsibilities include creating andtesting signal integrity and behavioral models of SRAMs, applicationssupport for customers, maintaining documentation and application notes,and board-level-failure-analysis debugging. His interests are developingGUIs in Labview, VB, and VC++; and FPGA-based designs. Email: .