Achronix hardens its FPGAs for PCI Express compliance -

Achronix hardens its FPGAs for PCI Express compliance

Achronix Semiconducto r  has achieved PCI-SIG compliance for the use of its 22 nm Speedster 22i asynchronous FPGAs in systems using the hardened PCI Express (PCIe) 3.0 Specification for x8 lanes.

According to Steve Mensor, Vice President of Marketing at Achronix, the Speedster22i devices successfully passed the PCI-SIG Compliance and Interoperability Tests at the PCI-SIG workshop and are now included in the PCI-SIG integrators list.

Fabricated on Intel’s 22nm Tri-gate technology, he said Speedster22i devices are the only FPGAs shipping today that contain a wide range of embedded hard IP – including PCI Express Gen3 with integrated DMA Engine, DDR3, 100G Ethernet and Interlaken.

Hardening key interface IP in the Speedster22i devices frees up a substantial portion of the programmable logic fabric, increasing the effective capacity of the FPGA and reducing the overall power consumption. Additionally the embedded hard IP in Speedster22i HD FPGAs eliminates the cost of purchasing, integrating, closing timing and testing the functions that are required when soft IP is used.

The PCI Express logic cores used in Speedster22i devices support Gen 1, 2 and 3 in x1, x4 and x8 configurations and are supplied by Northwest Logic. Speedster22i HD devices are the only FPGAs with an integrated DMA engine hardened as part of the PCI Express core. This provides additional cost, performance and power advantages vs. a soft implementation.

The now shipping Speedster22i HD1000 and HD680 FPGAs devices incorporate the following embedded hard IP: PCIe Gen3 x8 controllers, DDR 2/3 controllers, 10/40/100G Ethernet controllers and 12x10G Interlaken controllers.

Achronix FPGAs are built using a proprietary implementation of asynchronous self-timed circuit logic optimized for use in field programmable gate arrays. Asynchronous logic gates gates are not governed by a clock circuit or global clock signal and instead use signals that indicate completion of instructions and operations, specified by simple data transfer protocols.

Asynchronous circuits have the potential to be faster, and have advantages in lower power consumption, lower electromagnetic interference, and better modularity in large systems.

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