Actel develops architecture to remove communications bottlenecks -

Actel develops architecture to remove communications bottlenecks

Actel's Axcelerator family of field programmable gate arrays (FPGA) uses the company's new AX higher speed architecture and scalable platform.

The Axcelerator family is designed to eliminate the performance bottleneck created when FPGAs with traditionally slow internal core architectures are used in high-speed communications and bridging applications. Based on a 0.15m, seven-layer metal antifuse process, the devices range in density from 125,000 to 2million system gates and will deliver over 500MHz operation and up to 100% resource utilization.

The antifuse-based family is said to virtually eliminate extensive design optimization techniques required when using traditional SRAM-based FPGAs.

With 2million system gates, the largest device in this five-member family, the AX2000, contains support for up to 339kbits of embedded SRAM; 684 user I/Os; 10,752 dedicated flip flops; eight global clocks and eight phase-locked loops (PLLs).

The AX architecture and scalable platform exceeds 500MHz internal core performance. Its architectural advancements included an embedded FIFO controller with metastability immune control circuitry that supports high-performance communications design without using general device resources; a fully fracturable SuperCluster that allows high logic module utilization; an embedded 64bit/p in FIFO that eases interfacing with off-chip resources on different clock domains; a Core Tile structure that provides tighter clock skew across the device; and a flexible clock structure with eight PLLs and eight global clocks available equally across the chip that eliminates the need for clock floorplanning and eases design migration.

To complement Axcelerator's densities and performance, Actel has extended its intellectual property (IP) program by porting and optimizing more than 40 cores with additional support for high-performance interfaces available throughout the year. The program includes PCI-X, SPI 4.2, HyperTransport, Gigabit Ethernet, HDLC processors, forward error correction cores, a T1/E1 framer, a CRC generator and an 8-bit/10-bit encoder/decoder.

The Axcelerator family is supported by the Actel Libero 2.2 integrated design environment.

Published in Embedded Systems (Europe) September 2002

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